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stm32g474xx.h
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1
33#ifndef __STM32G474xx_H
34#define __STM32G474xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
65typedef enum
66{
67/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
68 NonMaskableInt_IRQn = -14,
69 HardFault_IRQn = -13,
70 MemoryManagement_IRQn = -12,
71 BusFault_IRQn = -11,
72 UsageFault_IRQn = -10,
73 SVCall_IRQn = -5,
74 DebugMonitor_IRQn = -4,
75 PendSV_IRQn = -2,
76 SysTick_IRQn = -1,
77/****** STM32 specific Interrupt Numbers ***************************************************************************************/
78 WWDG_IRQn = 0,
79 PVD_PVM_IRQn = 1,
80 RTC_TAMP_LSECSS_IRQn = 2,
81 RTC_WKUP_IRQn = 3,
82 FLASH_IRQn = 4,
83 RCC_IRQn = 5,
84 EXTI0_IRQn = 6,
85 EXTI1_IRQn = 7,
86 EXTI2_IRQn = 8,
87 EXTI3_IRQn = 9,
88 EXTI4_IRQn = 10,
89 DMA1_Channel1_IRQn = 11,
90 DMA1_Channel2_IRQn = 12,
91 DMA1_Channel3_IRQn = 13,
92 DMA1_Channel4_IRQn = 14,
93 DMA1_Channel5_IRQn = 15,
94 DMA1_Channel6_IRQn = 16,
95 DMA1_Channel7_IRQn = 17,
96 ADC1_2_IRQn = 18,
97 USB_HP_IRQn = 19,
98 USB_LP_IRQn = 20,
99 FDCAN1_IT0_IRQn = 21,
100 FDCAN1_IT1_IRQn = 22,
101 EXTI9_5_IRQn = 23,
102 TIM1_BRK_TIM15_IRQn = 24,
103 TIM1_UP_TIM16_IRQn = 25,
104 TIM1_TRG_COM_TIM17_IRQn = 26,
105 TIM1_CC_IRQn = 27,
106 TIM2_IRQn = 28,
107 TIM3_IRQn = 29,
108 TIM4_IRQn = 30,
109 I2C1_EV_IRQn = 31,
110 I2C1_ER_IRQn = 32,
111 I2C2_EV_IRQn = 33,
112 I2C2_ER_IRQn = 34,
113 SPI1_IRQn = 35,
114 SPI2_IRQn = 36,
115 USART1_IRQn = 37,
116 USART2_IRQn = 38,
117 USART3_IRQn = 39,
118 EXTI15_10_IRQn = 40,
119 RTC_Alarm_IRQn = 41,
120 USBWakeUp_IRQn = 42,
121 TIM8_BRK_IRQn = 43,
122 TIM8_UP_IRQn = 44,
123 TIM8_TRG_COM_IRQn = 45,
124 TIM8_CC_IRQn = 46,
125 ADC3_IRQn = 47,
126 FMC_IRQn = 48,
127 LPTIM1_IRQn = 49,
128 TIM5_IRQn = 50,
129 SPI3_IRQn = 51,
130 UART4_IRQn = 52,
131 UART5_IRQn = 53,
132 TIM6_DAC_IRQn = 54,
133 TIM7_DAC_IRQn = 55,
134 DMA2_Channel1_IRQn = 56,
135 DMA2_Channel2_IRQn = 57,
136 DMA2_Channel3_IRQn = 58,
137 DMA2_Channel4_IRQn = 59,
138 DMA2_Channel5_IRQn = 60,
139 ADC4_IRQn = 61,
140 ADC5_IRQn = 62,
141 UCPD1_IRQn = 63,
142 COMP1_2_3_IRQn = 64,
143 COMP4_5_6_IRQn = 65,
144 COMP7_IRQn = 66,
145 HRTIM1_Master_IRQn = 67,
146 HRTIM1_TIMA_IRQn = 68,
147 HRTIM1_TIMB_IRQn = 69,
148 HRTIM1_TIMC_IRQn = 70,
149 HRTIM1_TIMD_IRQn = 71,
150 HRTIM1_TIME_IRQn = 72,
151 HRTIM1_FLT_IRQn = 73,
152 HRTIM1_TIMF_IRQn = 74,
153 CRS_IRQn = 75,
154 SAI1_IRQn = 76,
155 TIM20_BRK_IRQn = 77,
156 TIM20_UP_IRQn = 78,
157 TIM20_TRG_COM_IRQn = 79,
158 TIM20_CC_IRQn = 80,
159 FPU_IRQn = 81,
160 I2C4_EV_IRQn = 82,
161 I2C4_ER_IRQn = 83,
162 SPI4_IRQn = 84,
163 FDCAN2_IT0_IRQn = 86,
164 FDCAN2_IT1_IRQn = 87,
165 FDCAN3_IT0_IRQn = 88,
166 FDCAN3_IT1_IRQn = 89,
167 RNG_IRQn = 90,
168 LPUART1_IRQn = 91,
169 I2C3_EV_IRQn = 92,
170 I2C3_ER_IRQn = 93,
171 DMAMUX_OVR_IRQn = 94,
172 QUADSPI_IRQn = 95,
173 DMA1_Channel8_IRQn = 96,
174 DMA2_Channel6_IRQn = 97,
175 DMA2_Channel7_IRQn = 98,
176 DMA2_Channel8_IRQn = 99,
177 CORDIC_IRQn = 100,
178 FMAC_IRQn = 101
179} IRQn_Type;
180
185#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
186#include "system_stm32g4xx.h"
187#include <stdint.h>
188
197typedef struct
198{
199 __IO uint32_t ISR;
200 __IO uint32_t IER;
201 __IO uint32_t CR;
202 __IO uint32_t CFGR;
203 __IO uint32_t CFGR2;
204 __IO uint32_t SMPR1;
205 __IO uint32_t SMPR2;
206 uint32_t RESERVED1;
207 __IO uint32_t TR1;
208 __IO uint32_t TR2;
209 __IO uint32_t TR3;
210 uint32_t RESERVED2;
211 __IO uint32_t SQR1;
212 __IO uint32_t SQR2;
213 __IO uint32_t SQR3;
214 __IO uint32_t SQR4;
215 __IO uint32_t DR;
216 uint32_t RESERVED3;
217 uint32_t RESERVED4;
218 __IO uint32_t JSQR;
219 uint32_t RESERVED5[4];
220 __IO uint32_t OFR1;
221 __IO uint32_t OFR2;
222 __IO uint32_t OFR3;
223 __IO uint32_t OFR4;
224 uint32_t RESERVED6[4];
225 __IO uint32_t JDR1;
226 __IO uint32_t JDR2;
227 __IO uint32_t JDR3;
228 __IO uint32_t JDR4;
229 uint32_t RESERVED7[4];
230 __IO uint32_t AWD2CR;
231 __IO uint32_t AWD3CR;
232 uint32_t RESERVED8;
233 uint32_t RESERVED9;
234 __IO uint32_t DIFSEL;
235 __IO uint32_t CALFACT;
236 uint32_t RESERVED10[2];
237 __IO uint32_t GCOMP;
238} ADC_TypeDef;
239
240typedef struct
241{
242 __IO uint32_t CSR;
243 uint32_t RESERVED1;
244 __IO uint32_t CCR;
245 __IO uint32_t CDR;
246} ADC_Common_TypeDef;
247
252typedef struct
253{
254 __IO uint32_t CREL;
255 __IO uint32_t ENDN;
256 uint32_t RESERVED1;
257 __IO uint32_t DBTP;
258 __IO uint32_t TEST;
259 __IO uint32_t RWD;
260 __IO uint32_t CCCR;
261 __IO uint32_t NBTP;
262 __IO uint32_t TSCC;
263 __IO uint32_t TSCV;
264 __IO uint32_t TOCC;
265 __IO uint32_t TOCV;
266 uint32_t RESERVED2[4];
267 __IO uint32_t ECR;
268 __IO uint32_t PSR;
269 __IO uint32_t TDCR;
270 uint32_t RESERVED3;
271 __IO uint32_t IR;
272 __IO uint32_t IE;
273 __IO uint32_t ILS;
274 __IO uint32_t ILE;
275 uint32_t RESERVED4[8];
276 __IO uint32_t RXGFC;
277 __IO uint32_t XIDAM;
278 __IO uint32_t HPMS;
279 uint32_t RESERVED5;
280 __IO uint32_t RXF0S;
281 __IO uint32_t RXF0A;
282 __IO uint32_t RXF1S;
283 __IO uint32_t RXF1A;
284 uint32_t RESERVED6[8];
285 __IO uint32_t TXBC;
286 __IO uint32_t TXFQS;
287 __IO uint32_t TXBRP;
288 __IO uint32_t TXBAR;
289 __IO uint32_t TXBCR;
290 __IO uint32_t TXBTO;
291 __IO uint32_t TXBCF;
292 __IO uint32_t TXBTIE;
293 __IO uint32_t TXBCIE;
294 __IO uint32_t TXEFS;
295 __IO uint32_t TXEFA;
296} FDCAN_GlobalTypeDef;
297
302typedef struct
303{
304 __IO uint32_t CKDIV;
305} FDCAN_Config_TypeDef;
306
311typedef struct
312{
313 __IO uint32_t CSR;
314} COMP_TypeDef;
315
320typedef struct
321{
322 __IO uint32_t DR;
323 __IO uint32_t IDR;
324 __IO uint32_t CR;
325 uint32_t RESERVED0;
326 __IO uint32_t INIT;
327 __IO uint32_t POL;
328} CRC_TypeDef;
329
333typedef struct
334{
335 __IO uint32_t CR;
336 __IO uint32_t CFGR;
337 __IO uint32_t ISR;
338 __IO uint32_t ICR;
339} CRS_TypeDef;
340
345typedef struct
346{
347 __IO uint32_t CR;
348 __IO uint32_t SWTRIGR;
349 __IO uint32_t DHR12R1;
350 __IO uint32_t DHR12L1;
351 __IO uint32_t DHR8R1;
352 __IO uint32_t DHR12R2;
353 __IO uint32_t DHR12L2;
354 __IO uint32_t DHR8R2;
355 __IO uint32_t DHR12RD;
356 __IO uint32_t DHR12LD;
357 __IO uint32_t DHR8RD;
358 __IO uint32_t DOR1;
359 __IO uint32_t DOR2;
360 __IO uint32_t SR;
361 __IO uint32_t CCR;
362 __IO uint32_t MCR;
363 __IO uint32_t SHSR1;
364 __IO uint32_t SHSR2;
365 __IO uint32_t SHHR;
366 __IO uint32_t SHRR;
367 __IO uint32_t RESERVED[2];
368 __IO uint32_t STR1;
369 __IO uint32_t STR2;
370 __IO uint32_t STMODR;
371} DAC_TypeDef;
372
377typedef struct
378{
379 __IO uint32_t IDCODE;
380 __IO uint32_t CR;
381 __IO uint32_t APB1FZR1;
382 __IO uint32_t APB1FZR2;
383 __IO uint32_t APB2FZ;
384} DBGMCU_TypeDef;
385
390typedef struct
391{
392 __IO uint32_t CCR;
393 __IO uint32_t CNDTR;
394 __IO uint32_t CPAR;
395 __IO uint32_t CMAR;
396} DMA_Channel_TypeDef;
397
398typedef struct
399{
400 __IO uint32_t ISR;
401 __IO uint32_t IFCR;
402} DMA_TypeDef;
403
408typedef struct
409{
410 __IO uint32_t CCR;
411}DMAMUX_Channel_TypeDef;
412
413typedef struct
414{
415 __IO uint32_t CSR;
416 __IO uint32_t CFR;
417}DMAMUX_ChannelStatus_TypeDef;
418
419typedef struct
420{
421 __IO uint32_t RGCR;
422}DMAMUX_RequestGen_TypeDef;
423
424typedef struct
425{
426 __IO uint32_t RGSR;
427 __IO uint32_t RGCFR;
428}DMAMUX_RequestGenStatus_TypeDef;
429
434typedef struct
435{
436 __IO uint32_t IMR1;
437 __IO uint32_t EMR1;
438 __IO uint32_t RTSR1;
439 __IO uint32_t FTSR1;
440 __IO uint32_t SWIER1;
441 __IO uint32_t PR1;
442 uint32_t RESERVED1;
443 uint32_t RESERVED2;
444 __IO uint32_t IMR2;
445 __IO uint32_t EMR2;
446 __IO uint32_t RTSR2;
447 __IO uint32_t FTSR2;
448 __IO uint32_t SWIER2;
449 __IO uint32_t PR2;
450} EXTI_TypeDef;
451
456typedef struct
457{
458 __IO uint32_t ACR;
459 __IO uint32_t PDKEYR;
460 __IO uint32_t KEYR;
461 __IO uint32_t OPTKEYR;
462 __IO uint32_t SR;
463 __IO uint32_t CR;
464 __IO uint32_t ECCR;
465 uint32_t RESERVED1;
466 __IO uint32_t OPTR;
467 __IO uint32_t PCROP1SR;
468 __IO uint32_t PCROP1ER;
469 __IO uint32_t WRP1AR;
470 __IO uint32_t WRP1BR;
471 uint32_t RESERVED2[4];
472 __IO uint32_t PCROP2SR;
473 __IO uint32_t PCROP2ER;
474 __IO uint32_t WRP2AR;
475 __IO uint32_t WRP2BR;
476 uint32_t RESERVED3[7];
477 __IO uint32_t SEC1R;
478 __IO uint32_t SEC2R;
479} FLASH_TypeDef;
480
484typedef struct
485{
486 __IO uint32_t X1BUFCFG;
487 __IO uint32_t X2BUFCFG;
488 __IO uint32_t YBUFCFG;
489 __IO uint32_t PARAM;
490 __IO uint32_t CR;
491 __IO uint32_t SR;
492 __IO uint32_t WDATA;
493 __IO uint32_t RDATA;
494} FMAC_TypeDef;
495
500typedef struct
501{
502 __IO uint32_t BTCR[8];
503 __IO uint32_t PCSCNTR;
504} FMC_Bank1_TypeDef;
505
510typedef struct
511{
512 __IO uint32_t BWTR[7];
513} FMC_Bank1E_TypeDef;
514
519typedef struct
520{
521 __IO uint32_t PCR;
522 __IO uint32_t SR;
523 __IO uint32_t PMEM;
524 __IO uint32_t PATT;
525 uint32_t RESERVED0;
526 __IO uint32_t ECCR;
527} FMC_Bank3_TypeDef;
528
533typedef struct
534{
535 __IO uint32_t MODER;
536 __IO uint32_t OTYPER;
537 __IO uint32_t OSPEEDR;
538 __IO uint32_t PUPDR;
539 __IO uint32_t IDR;
540 __IO uint32_t ODR;
541 __IO uint32_t BSRR;
542 __IO uint32_t LCKR;
543 __IO uint32_t AFR[2];
544 __IO uint32_t BRR;
545} GPIO_TypeDef;
546
551typedef struct
552{
553 __IO uint32_t CR1;
554 __IO uint32_t CR2;
555 __IO uint32_t OAR1;
556 __IO uint32_t OAR2;
557 __IO uint32_t TIMINGR;
558 __IO uint32_t TIMEOUTR;
559 __IO uint32_t ISR;
560 __IO uint32_t ICR;
561 __IO uint32_t PECR;
562 __IO uint32_t RXDR;
563 __IO uint32_t TXDR;
564} I2C_TypeDef;
565
570typedef struct
571{
572 __IO uint32_t KR;
573 __IO uint32_t PR;
574 __IO uint32_t RLR;
575 __IO uint32_t SR;
576 __IO uint32_t WINR;
577} IWDG_TypeDef;
578
583typedef struct
584{
585 __IO uint32_t ISR;
586 __IO uint32_t ICR;
587 __IO uint32_t IER;
588 __IO uint32_t CFGR;
589 __IO uint32_t CR;
590 __IO uint32_t CMP;
591 __IO uint32_t ARR;
592 __IO uint32_t CNT;
593 __IO uint32_t OR;
594} LPTIM_TypeDef;
595
600typedef struct
601{
602 __IO uint32_t CSR;
603 __IO uint32_t RESERVED[5];
604 __IO uint32_t TCMR;
605} OPAMP_TypeDef;
606
611typedef struct
612{
613 __IO uint32_t CR1;
614 __IO uint32_t CR2;
615 __IO uint32_t CR3;
616 __IO uint32_t CR4;
617 __IO uint32_t SR1;
618 __IO uint32_t SR2;
619 __IO uint32_t SCR;
620 uint32_t RESERVED;
621 __IO uint32_t PUCRA;
622 __IO uint32_t PDCRA;
623 __IO uint32_t PUCRB;
624 __IO uint32_t PDCRB;
625 __IO uint32_t PUCRC;
626 __IO uint32_t PDCRC;
627 __IO uint32_t PUCRD;
628 __IO uint32_t PDCRD;
629 __IO uint32_t PUCRE;
630 __IO uint32_t PDCRE;
631 __IO uint32_t PUCRF;
632 __IO uint32_t PDCRF;
633 __IO uint32_t PUCRG;
634 __IO uint32_t PDCRG;
635 uint32_t RESERVED1[10];
636 __IO uint32_t CR5;
637} PWR_TypeDef;
638
643typedef struct
644{
645 __IO uint32_t CR;
646 __IO uint32_t DCR;
647 __IO uint32_t SR;
648 __IO uint32_t FCR;
649 __IO uint32_t DLR;
650 __IO uint32_t CCR;
651 __IO uint32_t AR;
652 __IO uint32_t ABR;
653 __IO uint32_t DR;
654 __IO uint32_t PSMKR;
655 __IO uint32_t PSMAR;
656 __IO uint32_t PIR;
657 __IO uint32_t LPTR;
658} QUADSPI_TypeDef;
659
664typedef struct
665{
666 __IO uint32_t CR;
667 __IO uint32_t ICSCR;
668 __IO uint32_t CFGR;
669 __IO uint32_t PLLCFGR;
670 uint32_t RESERVED0;
671 uint32_t RESERVED1;
672 __IO uint32_t CIER;
673 __IO uint32_t CIFR;
674 __IO uint32_t CICR;
675 uint32_t RESERVED2;
676 __IO uint32_t AHB1RSTR;
677 __IO uint32_t AHB2RSTR;
678 __IO uint32_t AHB3RSTR;
679 uint32_t RESERVED3;
680 __IO uint32_t APB1RSTR1;
681 __IO uint32_t APB1RSTR2;
682 __IO uint32_t APB2RSTR;
683 uint32_t RESERVED4;
684 __IO uint32_t AHB1ENR;
685 __IO uint32_t AHB2ENR;
686 __IO uint32_t AHB3ENR;
687 uint32_t RESERVED5;
688 __IO uint32_t APB1ENR1;
689 __IO uint32_t APB1ENR2;
690 __IO uint32_t APB2ENR;
691 uint32_t RESERVED6;
692 __IO uint32_t AHB1SMENR;
693 __IO uint32_t AHB2SMENR;
694 __IO uint32_t AHB3SMENR;
695 uint32_t RESERVED7;
696 __IO uint32_t APB1SMENR1;
697 __IO uint32_t APB1SMENR2;
698 __IO uint32_t APB2SMENR;
699 uint32_t RESERVED8;
700 __IO uint32_t CCIPR;
701 uint32_t RESERVED9;
702 __IO uint32_t BDCR;
703 __IO uint32_t CSR;
704 __IO uint32_t CRRCR;
705 __IO uint32_t CCIPR2;
706} RCC_TypeDef;
707
711/*
712* @brief Specific device feature definitions
713*/
714#define RTC_TAMP_INT_6_SUPPORT
715#define RTC_TAMP_INT_NB 4u
716
717#define RTC_TAMP_NB 3u
718#define RTC_BACKUP_NB 32u
719
720
721typedef struct
722{
723 __IO uint32_t TR;
724 __IO uint32_t DR;
725 __IO uint32_t SSR;
726 __IO uint32_t ICSR;
727 __IO uint32_t PRER;
728 __IO uint32_t WUTR;
729 __IO uint32_t CR;
730 uint32_t RESERVED0;
731 uint32_t RESERVED1;
732 __IO uint32_t WPR;
733 __IO uint32_t CALR;
734 __IO uint32_t SHIFTR;
735 __IO uint32_t TSTR;
736 __IO uint32_t TSDR;
737 __IO uint32_t TSSSR;
738 uint32_t RESERVED2;
739 __IO uint32_t ALRMAR;
740 __IO uint32_t ALRMASSR;
741 __IO uint32_t ALRMBR;
742 __IO uint32_t ALRMBSSR;
743 __IO uint32_t SR;
744 __IO uint32_t MISR;
745 uint32_t RESERVED3;
746 __IO uint32_t SCR;
747} RTC_TypeDef;
748
753typedef struct
754{
755 __IO uint32_t CR1;
756 __IO uint32_t CR2;
757 uint32_t RESERVED0;
758 __IO uint32_t FLTCR;
759 uint32_t RESERVED1[6];
760 uint32_t RESERVED2;
761 __IO uint32_t IER;
762 __IO uint32_t SR;
763 __IO uint32_t MISR;
764 uint32_t RESERVED3;
765 __IO uint32_t SCR;
766 uint32_t RESERVED4[48];
767 __IO uint32_t BKP0R;
768 __IO uint32_t BKP1R;
769 __IO uint32_t BKP2R;
770 __IO uint32_t BKP3R;
771 __IO uint32_t BKP4R;
772 __IO uint32_t BKP5R;
773 __IO uint32_t BKP6R;
774 __IO uint32_t BKP7R;
775 __IO uint32_t BKP8R;
776 __IO uint32_t BKP9R;
777 __IO uint32_t BKP10R;
778 __IO uint32_t BKP11R;
779 __IO uint32_t BKP12R;
780 __IO uint32_t BKP13R;
781 __IO uint32_t BKP14R;
782 __IO uint32_t BKP15R;
783 __IO uint32_t BKP16R;
784 __IO uint32_t BKP17R;
785 __IO uint32_t BKP18R;
786 __IO uint32_t BKP19R;
787 __IO uint32_t BKP20R;
788 __IO uint32_t BKP21R;
789 __IO uint32_t BKP22R;
790 __IO uint32_t BKP23R;
791 __IO uint32_t BKP24R;
792 __IO uint32_t BKP25R;
793 __IO uint32_t BKP26R;
794 __IO uint32_t BKP27R;
795 __IO uint32_t BKP28R;
796 __IO uint32_t BKP29R;
797 __IO uint32_t BKP30R;
798 __IO uint32_t BKP31R;
799} TAMP_TypeDef;
800
805typedef struct
806{
807 __IO uint32_t GCR;
808 uint32_t RESERVED[16];
809 __IO uint32_t PDMCR;
810 __IO uint32_t PDMDLY;
811} SAI_TypeDef;
812
813typedef struct
814{
815 __IO uint32_t CR1;
816 __IO uint32_t CR2;
817 __IO uint32_t FRCR;
818 __IO uint32_t SLOTR;
819 __IO uint32_t IMR;
820 __IO uint32_t SR;
821 __IO uint32_t CLRFR;
822 __IO uint32_t DR;
823} SAI_Block_TypeDef;
824
829typedef struct
830{
831 __IO uint32_t CR1;
832 __IO uint32_t CR2;
833 __IO uint32_t SR;
834 __IO uint32_t DR;
835 __IO uint32_t CRCPR;
836 __IO uint32_t RXCRCR;
837 __IO uint32_t TXCRCR;
838 __IO uint32_t I2SCFGR;
839 __IO uint32_t I2SPR;
840} SPI_TypeDef;
841
846typedef struct
847{
848 __IO uint32_t MEMRMP;
849 __IO uint32_t CFGR1;
850 __IO uint32_t EXTICR[4];
851 __IO uint32_t SCSR;
852 __IO uint32_t CFGR2;
853 __IO uint32_t SWPR;
854 __IO uint32_t SKR;
855} SYSCFG_TypeDef;
856
861typedef struct
862{
863 __IO uint32_t CR1;
864 __IO uint32_t CR2;
865 __IO uint32_t SMCR;
866 __IO uint32_t DIER;
867 __IO uint32_t SR;
868 __IO uint32_t EGR;
869 __IO uint32_t CCMR1;
870 __IO uint32_t CCMR2;
871 __IO uint32_t CCER;
872 __IO uint32_t CNT;
873 __IO uint32_t PSC;
874 __IO uint32_t ARR;
875 __IO uint32_t RCR;
876 __IO uint32_t CCR1;
877 __IO uint32_t CCR2;
878 __IO uint32_t CCR3;
879 __IO uint32_t CCR4;
880 __IO uint32_t BDTR;
881 __IO uint32_t CCR5;
882 __IO uint32_t CCR6;
883 __IO uint32_t CCMR3;
884 __IO uint32_t DTR2;
885 __IO uint32_t ECR;
886 __IO uint32_t TISEL;
887 __IO uint32_t AF1;
888 __IO uint32_t AF2;
889 __IO uint32_t OR ;
890 uint32_t RESERVED0[220];
891 __IO uint32_t DCR;
892 __IO uint32_t DMAR;
893} TIM_TypeDef;
894
898typedef struct
899{
900 __IO uint32_t CR1;
901 __IO uint32_t CR2;
902 __IO uint32_t CR3;
903 __IO uint32_t BRR;
904 __IO uint32_t GTPR;
905 __IO uint32_t RTOR;
906 __IO uint32_t RQR;
907 __IO uint32_t ISR;
908 __IO uint32_t ICR;
909 __IO uint32_t RDR;
910 __IO uint32_t TDR;
911 __IO uint32_t PRESC;
912} USART_TypeDef;
913
918typedef struct
919{
920 __IO uint16_t EP0R;
921 __IO uint16_t RESERVED0;
922 __IO uint16_t EP1R;
923 __IO uint16_t RESERVED1;
924 __IO uint16_t EP2R;
925 __IO uint16_t RESERVED2;
926 __IO uint16_t EP3R;
927 __IO uint16_t RESERVED3;
928 __IO uint16_t EP4R;
929 __IO uint16_t RESERVED4;
930 __IO uint16_t EP5R;
931 __IO uint16_t RESERVED5;
932 __IO uint16_t EP6R;
933 __IO uint16_t RESERVED6;
934 __IO uint16_t EP7R;
935 __IO uint16_t RESERVED7[17];
936 __IO uint16_t CNTR;
937 __IO uint16_t RESERVED8;
938 __IO uint16_t ISTR;
939 __IO uint16_t RESERVED9;
940 __IO uint16_t FNR;
941 __IO uint16_t RESERVEDA;
942 __IO uint16_t DADDR;
943 __IO uint16_t RESERVEDB;
944 __IO uint16_t BTABLE;
945 __IO uint16_t RESERVEDC;
946 __IO uint16_t LPMCSR;
947 __IO uint16_t RESERVEDD;
948 __IO uint16_t BCDR;
949 __IO uint16_t RESERVEDE;
950} USB_TypeDef;
951
956typedef struct
957{
958 __IO uint32_t CSR;
959 __IO uint32_t CCR;
960} VREFBUF_TypeDef;
961
966typedef struct
967{
968 __IO uint32_t CR;
969 __IO uint32_t CFR;
970 __IO uint32_t SR;
971} WWDG_TypeDef;
972
973
977typedef struct
978{
979 __IO uint32_t CR;
980 __IO uint32_t SR;
981 __IO uint32_t DR;
982} RNG_TypeDef;
983
988typedef struct
989{
990 __IO uint32_t CSR;
991 __IO uint32_t WDATA;
992 __IO uint32_t RDATA;
993} CORDIC_TypeDef;
994
999typedef struct
1000{
1001 __IO uint32_t CFG1;
1002 __IO uint32_t CFG2;
1003 __IO uint32_t RESERVED0;
1004 __IO uint32_t CR;
1005 __IO uint32_t IMR;
1006 __IO uint32_t SR;
1007 __IO uint32_t ICR;
1008 __IO uint32_t TX_ORDSET;
1009 __IO uint32_t TX_PAYSZ;
1010 __IO uint32_t TXDR;
1011 __IO uint32_t RX_ORDSET;
1012 __IO uint32_t RX_PAYSZ;
1013 __IO uint32_t RXDR;
1014 __IO uint32_t RX_ORDEXT1;
1015 __IO uint32_t RX_ORDEXT2;
1016} UCPD_TypeDef;
1017
1022#define c7amba_hrtim1_v2_0
1023
1024/* HRTIM master registers definition */
1025typedef struct
1026{
1027 __IO uint32_t MCR;
1028 __IO uint32_t MISR;
1029 __IO uint32_t MICR;
1030 __IO uint32_t MDIER;
1031 __IO uint32_t MCNTR;
1032 __IO uint32_t MPER;
1033 __IO uint32_t MREP;
1034 __IO uint32_t MCMP1R;
1035 uint32_t RESERVED0;
1036 __IO uint32_t MCMP2R;
1037 __IO uint32_t MCMP3R;
1038 __IO uint32_t MCMP4R;
1039 uint32_t RESERVED1[20];
1040}HRTIM_Master_TypeDef;
1041
1042/* HRTIM Timer A to F registers definition */
1043typedef struct
1044{
1045 __IO uint32_t TIMxCR;
1046 __IO uint32_t TIMxISR;
1047 __IO uint32_t TIMxICR;
1048 __IO uint32_t TIMxDIER;
1049 __IO uint32_t CNTxR;
1050 __IO uint32_t PERxR;
1051 __IO uint32_t REPxR;
1052 __IO uint32_t CMP1xR;
1053 __IO uint32_t CMP1CxR;
1054 __IO uint32_t CMP2xR;
1055 __IO uint32_t CMP3xR;
1056 __IO uint32_t CMP4xR;
1057 __IO uint32_t CPT1xR;
1058 __IO uint32_t CPT2xR;
1059 __IO uint32_t DTxR;
1060 __IO uint32_t SETx1R;
1061 __IO uint32_t RSTx1R;
1062 __IO uint32_t SETx2R;
1063 __IO uint32_t RSTx2R;
1064 __IO uint32_t EEFxR1;
1065 __IO uint32_t EEFxR2;
1066 __IO uint32_t RSTxR;
1067 __IO uint32_t CHPxR;
1068 __IO uint32_t CPT1xCR;
1069 __IO uint32_t CPT2xCR;
1070 __IO uint32_t OUTxR;
1071 __IO uint32_t FLTxR;
1072 __IO uint32_t TIMxCR2;
1073 __IO uint32_t EEFxR3;
1074 uint32_t RESERVED0[3];
1075}HRTIM_Timerx_TypeDef;
1076
1077/* HRTIM common register definition */
1078typedef struct
1079{
1080 __IO uint32_t CR1;
1081 __IO uint32_t CR2;
1082 __IO uint32_t ISR;
1083 __IO uint32_t ICR;
1084 __IO uint32_t IER;
1085 __IO uint32_t OENR;
1086 __IO uint32_t ODISR;
1087 __IO uint32_t ODSR;
1088 __IO uint32_t BMCR;
1089 __IO uint32_t BMTRGR;
1090 __IO uint32_t BMCMPR;
1091 __IO uint32_t BMPER;
1092 __IO uint32_t EECR1;
1093 __IO uint32_t EECR2;
1094 __IO uint32_t EECR3;
1095 __IO uint32_t ADC1R;
1096 __IO uint32_t ADC2R;
1097 __IO uint32_t ADC3R;
1098 __IO uint32_t ADC4R;
1099 __IO uint32_t DLLCR;
1100 __IO uint32_t FLTINR1;
1101 __IO uint32_t FLTINR2;
1102 __IO uint32_t BDMUPR;
1103 __IO uint32_t BDTAUPR;
1104 __IO uint32_t BDTBUPR;
1105 __IO uint32_t BDTCUPR;
1106 __IO uint32_t BDTDUPR;
1107 __IO uint32_t BDTEUPR;
1108 __IO uint32_t BDMADR;
1109 __IO uint32_t BDTFUPR;
1110 __IO uint32_t ADCER;
1111 __IO uint32_t ADCUR;
1112 __IO uint32_t ADCPS1;
1113 __IO uint32_t ADCPS2;
1114 __IO uint32_t FLTINR3;
1115 __IO uint32_t FLTINR4;
1116}HRTIM_Common_TypeDef;
1117
1118/* HRTIM register definition */
1119typedef struct {
1120 HRTIM_Master_TypeDef sMasterRegs;
1121 HRTIM_Timerx_TypeDef sTimerxRegs[6];
1122 HRTIM_Common_TypeDef sCommonRegs;
1123}HRTIM_TypeDef;
1124
1133#define FLASH_BASE (0x08000000UL)
1134#define SRAM1_BASE (0x20000000UL)
1135#define SRAM2_BASE (0x20014000UL)
1136#define CCMSRAM_BASE (0x10000000UL)
1137#define PERIPH_BASE (0x40000000UL)
1138#define FMC_BASE (0x60000000UL)
1139#define QSPI_BASE (0x90000000UL)
1141#define FMC_R_BASE (0xA0000000UL)
1142#define QSPI_R_BASE (0xA0001000UL)
1143#define SRAM1_BB_BASE (0x22000000UL)
1144#define SRAM2_BB_BASE (0x22280000UL)
1145#define CCMSRAM_BB_BASE (0x22300000UL)
1146#define PERIPH_BB_BASE (0x42000000UL)
1147/* Legacy defines */
1148#define SRAM_BASE SRAM1_BASE
1149#define SRAM_BB_BASE SRAM1_BB_BASE
1150
1151#define SRAM1_SIZE_MAX (0x00014000UL)
1152#define SRAM2_SIZE (0x00004000UL)
1153#define CCMSRAM_SIZE (0x00008000UL)
1156#define APB1PERIPH_BASE PERIPH_BASE
1157#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1158#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1159#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
1160
1161#define FMC_BANK1 FMC_BASE
1162#define FMC_BANK1_1 FMC_BANK1
1163#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
1164#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
1165#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
1166#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
1167
1169#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1170#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1171#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1172#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1173#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1174#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1175#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
1176#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
1177#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1178#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1179#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1180#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1181#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1182#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1183#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1184#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1185#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1186#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1187#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1188#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL)
1189#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL)
1190#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1191#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL)
1192#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1193#define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL)
1194#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1195#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
1196#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
1197#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
1198#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
1199#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
1200#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
1201
1203#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
1204#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
1205#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
1206#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
1207#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
1208#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
1209#define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL)
1210#define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL)
1211#define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL)
1212#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
1213#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
1214#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
1215#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
1216#define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL)
1217#define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL)
1218#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)
1219
1220#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
1221#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1222#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1223#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
1224#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
1225#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL)
1226#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
1227#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
1228#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
1229#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
1230#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
1231#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
1232#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
1233#define HRTIM1_BASE (APB2PERIPH_BASE + 0x6800UL)
1234#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x0080UL)
1235#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x0100UL)
1236#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x0180UL)
1237#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x0200UL)
1238#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x0280UL)
1239#define HRTIM1_TIMF_BASE (HRTIM1_BASE + 0x0300UL)
1240#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x0380UL)
1241
1243#define DMA1_BASE (AHB1PERIPH_BASE)
1244#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
1245#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
1246#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1247#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
1248#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
1249#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
1250#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1251
1252#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
1253#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
1254#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
1255#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
1256#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1257#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1258#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
1259#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)
1260
1261#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
1262#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
1263#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
1264#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
1265#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
1266#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
1267#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
1268#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
1269
1270#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
1271#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
1272#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
1273#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
1274#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
1275#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
1276#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
1277#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
1278#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
1279#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
1280#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
1281#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
1282#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
1283#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
1284#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
1285#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
1286#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
1287#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
1288#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
1289#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
1290
1291#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
1292#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
1293
1295#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
1296#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
1297#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
1298#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
1299#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
1300#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
1301#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
1302
1303#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
1304#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
1305#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
1306#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)
1307#define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL)
1308#define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL)
1309#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)
1310
1311#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
1312#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
1313#define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL)
1314#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
1315#define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL)
1316
1318#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1319#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1320#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1321#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
1322/* Debug MCU registers base address */
1323#define DBGMCU_BASE (0xE0042000UL)
1324
1325#define PACKAGE_BASE (0x1FFF7500UL)
1326#define UID_BASE (0x1FFF7590UL)
1327#define FLASHSIZE_BASE (0x1FFF75E0UL)
1335#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1336#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1337#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1338#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1339#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1340#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1341#define CRS ((CRS_TypeDef *) CRS_BASE)
1342#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
1343#define RTC ((RTC_TypeDef *) RTC_BASE)
1344#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1345#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1346#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1347#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1348#define USART2 ((USART_TypeDef *) USART2_BASE)
1349#define USART3 ((USART_TypeDef *) USART3_BASE)
1350#define UART4 ((USART_TypeDef *) UART4_BASE)
1351#define UART5 ((USART_TypeDef *) UART5_BASE)
1352#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1353#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1354#define USB ((USB_TypeDef *) USB_BASE)
1355#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
1356#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
1357#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
1358#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
1359#define PWR ((PWR_TypeDef *) PWR_BASE)
1360#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1361#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1362#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1363#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1364#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
1365
1366#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1367#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1368#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1369#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1370#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
1371#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
1372#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
1373#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
1374#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
1375
1376#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1377#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1378#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1379#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
1380#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
1381#define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE)
1382#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)
1383
1384#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1385#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1386#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1387#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1388#define USART1 ((USART_TypeDef *) USART1_BASE)
1389#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1390#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1391#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1392#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1393#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
1394#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1395#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1396#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1397#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
1398#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
1399#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
1400#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
1401#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
1402#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
1403#define HRTIM1_TIMF ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMF_BASE)
1404#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
1405#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1406#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1407#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1408#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
1409#define RCC ((RCC_TypeDef *) RCC_BASE)
1410#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
1411#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1412#define CRC ((CRC_TypeDef *) CRC_BASE)
1413
1414#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1415#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1416#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1417#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1418#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1419#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1420#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1421#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1422#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1423#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1424#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1425#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
1426#define ADC5 ((ADC_TypeDef *) ADC5_BASE)
1427#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
1428#define DAC ((DAC_TypeDef *) DAC_BASE)
1429#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1430#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
1431#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
1432#define DAC4 ((DAC_TypeDef *) DAC4_BASE)
1433#define RNG ((RNG_TypeDef *) RNG_BASE)
1434
1435#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1436#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1437#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1438#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1439#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1440#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1441#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1442#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
1443
1444#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1445#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1446#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1447#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1448#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1449#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1450#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1451#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
1452
1453#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1454#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1455#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1456#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1457#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1458#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1459#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1460#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1461#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1462#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1463#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1464#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1465#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1466#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1467#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
1468#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
1469
1470#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1471#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1472#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1473#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1474
1475#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1476#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1477
1478#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1479#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1480#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1481
1482#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1483
1484#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1485
1497#define LSI_STARTUP_TIME 130U
1507/******************************************************************************/
1508/* Peripheral Registers_Bits_Definition */
1509/******************************************************************************/
1510
1511/******************************************************************************/
1512/* */
1513/* Analog to Digital Converter */
1514/* */
1515/******************************************************************************/
1516
1517/*
1518 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
1519 */
1520#define ADC_MULTIMODE_SUPPORT
1522/******************** Bit definition for ADC_ISR register *******************/
1523#define ADC_ISR_ADRDY_Pos (0U)
1524#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
1525#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
1526#define ADC_ISR_EOSMP_Pos (1U)
1527#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
1528#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
1529#define ADC_ISR_EOC_Pos (2U)
1530#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
1531#define ADC_ISR_EOC ADC_ISR_EOC_Msk
1532#define ADC_ISR_EOS_Pos (3U)
1533#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
1534#define ADC_ISR_EOS ADC_ISR_EOS_Msk
1535#define ADC_ISR_OVR_Pos (4U)
1536#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
1537#define ADC_ISR_OVR ADC_ISR_OVR_Msk
1538#define ADC_ISR_JEOC_Pos (5U)
1539#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
1540#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
1541#define ADC_ISR_JEOS_Pos (6U)
1542#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
1543#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
1544#define ADC_ISR_AWD1_Pos (7U)
1545#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
1546#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
1547#define ADC_ISR_AWD2_Pos (8U)
1548#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
1549#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
1550#define ADC_ISR_AWD3_Pos (9U)
1551#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
1552#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
1553#define ADC_ISR_JQOVF_Pos (10U)
1554#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
1555#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
1557/******************** Bit definition for ADC_IER register *******************/
1558#define ADC_IER_ADRDYIE_Pos (0U)
1559#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
1560#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
1561#define ADC_IER_EOSMPIE_Pos (1U)
1562#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
1563#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
1564#define ADC_IER_EOCIE_Pos (2U)
1565#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
1566#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
1567#define ADC_IER_EOSIE_Pos (3U)
1568#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
1569#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
1570#define ADC_IER_OVRIE_Pos (4U)
1571#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
1572#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
1573#define ADC_IER_JEOCIE_Pos (5U)
1574#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
1575#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
1576#define ADC_IER_JEOSIE_Pos (6U)
1577#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
1578#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
1579#define ADC_IER_AWD1IE_Pos (7U)
1580#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
1581#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
1582#define ADC_IER_AWD2IE_Pos (8U)
1583#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
1584#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
1585#define ADC_IER_AWD3IE_Pos (9U)
1586#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
1587#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
1588#define ADC_IER_JQOVFIE_Pos (10U)
1589#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
1590#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
1592/******************** Bit definition for ADC_CR register ********************/
1593#define ADC_CR_ADEN_Pos (0U)
1594#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
1595#define ADC_CR_ADEN ADC_CR_ADEN_Msk
1596#define ADC_CR_ADDIS_Pos (1U)
1597#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
1598#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
1599#define ADC_CR_ADSTART_Pos (2U)
1600#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
1601#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
1602#define ADC_CR_JADSTART_Pos (3U)
1603#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
1604#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
1605#define ADC_CR_ADSTP_Pos (4U)
1606#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
1607#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
1608#define ADC_CR_JADSTP_Pos (5U)
1609#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
1610#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
1611#define ADC_CR_ADVREGEN_Pos (28U)
1612#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
1613#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
1614#define ADC_CR_DEEPPWD_Pos (29U)
1615#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
1616#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
1617#define ADC_CR_ADCALDIF_Pos (30U)
1618#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
1619#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
1620#define ADC_CR_ADCAL_Pos (31U)
1621#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
1622#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
1624/******************** Bit definition for ADC_CFGR register ******************/
1625#define ADC_CFGR_DMAEN_Pos (0U)
1626#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)
1627#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk
1628#define ADC_CFGR_DMACFG_Pos (1U)
1629#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)
1630#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk
1632#define ADC_CFGR_RES_Pos (3U)
1633#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)
1634#define ADC_CFGR_RES ADC_CFGR_RES_Msk
1635#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
1636#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
1638#define ADC_CFGR_EXTSEL_Pos (5U)
1639#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)
1640#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
1641#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)
1642#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)
1643#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)
1644#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)
1645#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)
1647#define ADC_CFGR_EXTEN_Pos (10U)
1648#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
1649#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
1650#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
1651#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
1653#define ADC_CFGR_OVRMOD_Pos (12U)
1654#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
1655#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
1656#define ADC_CFGR_CONT_Pos (13U)
1657#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
1658#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
1659#define ADC_CFGR_AUTDLY_Pos (14U)
1660#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
1661#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
1662#define ADC_CFGR_ALIGN_Pos (15U)
1663#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)
1664#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk
1665#define ADC_CFGR_DISCEN_Pos (16U)
1666#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
1667#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
1669#define ADC_CFGR_DISCNUM_Pos (17U)
1670#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
1671#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
1672#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
1673#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
1674#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
1676#define ADC_CFGR_JDISCEN_Pos (20U)
1677#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
1678#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
1679#define ADC_CFGR_JQM_Pos (21U)
1680#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
1681#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
1682#define ADC_CFGR_AWD1SGL_Pos (22U)
1683#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
1684#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
1685#define ADC_CFGR_AWD1EN_Pos (23U)
1686#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
1687#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
1688#define ADC_CFGR_JAWD1EN_Pos (24U)
1689#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
1690#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
1691#define ADC_CFGR_JAUTO_Pos (25U)
1692#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
1693#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
1695#define ADC_CFGR_AWD1CH_Pos (26U)
1696#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
1697#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
1698#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
1699#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
1700#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
1701#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
1702#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
1704#define ADC_CFGR_JQDIS_Pos (31U)
1705#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
1706#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
1708/******************** Bit definition for ADC_CFGR2 register *****************/
1709#define ADC_CFGR2_ROVSE_Pos (0U)
1710#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
1711#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
1712#define ADC_CFGR2_JOVSE_Pos (1U)
1713#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
1714#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
1716#define ADC_CFGR2_OVSR_Pos (2U)
1717#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)
1718#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
1719#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)
1720#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)
1721#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)
1723#define ADC_CFGR2_OVSS_Pos (5U)
1724#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
1725#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
1726#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
1727#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
1728#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
1729#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
1731#define ADC_CFGR2_TROVS_Pos (9U)
1732#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
1733#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
1734#define ADC_CFGR2_ROVSM_Pos (10U)
1735#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
1736#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
1738#define ADC_CFGR2_GCOMP_Pos (16U)
1739#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos)
1740#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk
1742#define ADC_CFGR2_SWTRIG_Pos (25U)
1743#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos)
1744#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk
1745#define ADC_CFGR2_BULB_Pos (26U)
1746#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos)
1747#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk
1748#define ADC_CFGR2_SMPTRIG_Pos (27U)
1749#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos)
1750#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk
1752/******************** Bit definition for ADC_SMPR1 register *****************/
1753#define ADC_SMPR1_SMP0_Pos (0U)
1754#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
1755#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
1756#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
1757#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
1758#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
1760#define ADC_SMPR1_SMP1_Pos (3U)
1761#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
1762#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
1763#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
1764#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
1765#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
1767#define ADC_SMPR1_SMP2_Pos (6U)
1768#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
1769#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
1770#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
1771#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
1772#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
1774#define ADC_SMPR1_SMP3_Pos (9U)
1775#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
1776#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
1777#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
1778#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
1779#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
1781#define ADC_SMPR1_SMP4_Pos (12U)
1782#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
1783#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
1784#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
1785#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
1786#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
1788#define ADC_SMPR1_SMP5_Pos (15U)
1789#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
1790#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
1791#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
1792#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
1793#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
1795#define ADC_SMPR1_SMP6_Pos (18U)
1796#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
1797#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
1798#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
1799#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
1800#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
1802#define ADC_SMPR1_SMP7_Pos (21U)
1803#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
1804#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
1805#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
1806#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
1807#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
1809#define ADC_SMPR1_SMP8_Pos (24U)
1810#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
1811#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
1812#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
1813#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
1814#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
1816#define ADC_SMPR1_SMP9_Pos (27U)
1817#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
1818#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
1819#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
1820#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
1821#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
1823#define ADC_SMPR1_SMPPLUS_Pos (31U)
1824#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos)
1825#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk
1827/******************** Bit definition for ADC_SMPR2 register *****************/
1828#define ADC_SMPR2_SMP10_Pos (0U)
1829#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
1830#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
1831#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
1832#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
1833#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
1835#define ADC_SMPR2_SMP11_Pos (3U)
1836#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
1837#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
1838#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
1839#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
1840#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
1842#define ADC_SMPR2_SMP12_Pos (6U)
1843#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
1844#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
1845#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
1846#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
1847#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
1849#define ADC_SMPR2_SMP13_Pos (9U)
1850#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
1851#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
1852#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
1853#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
1854#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
1856#define ADC_SMPR2_SMP14_Pos (12U)
1857#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
1858#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
1859#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
1860#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
1861#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
1863#define ADC_SMPR2_SMP15_Pos (15U)
1864#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
1865#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
1866#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
1867#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
1868#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
1870#define ADC_SMPR2_SMP16_Pos (18U)
1871#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
1872#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
1873#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
1874#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
1875#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
1877#define ADC_SMPR2_SMP17_Pos (21U)
1878#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
1879#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
1880#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
1881#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
1882#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
1884#define ADC_SMPR2_SMP18_Pos (24U)
1885#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
1886#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
1887#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
1888#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
1889#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
1891/******************** Bit definition for ADC_TR1 register *******************/
1892#define ADC_TR1_LT1_Pos (0U)
1893#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)
1894#define ADC_TR1_LT1 ADC_TR1_LT1_Msk
1896#define ADC_TR1_AWDFILT_Pos (12U)
1897#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos)
1898#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk
1899#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos)
1900#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos)
1901#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos)
1903#define ADC_TR1_HT1_Pos (16U)
1904#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)
1905#define ADC_TR1_HT1 ADC_TR1_HT1_Msk
1907/******************** Bit definition for ADC_TR2 register *******************/
1908#define ADC_TR2_LT2_Pos (0U)
1909#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)
1910#define ADC_TR2_LT2 ADC_TR2_LT2_Msk
1912#define ADC_TR2_HT2_Pos (16U)
1913#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)
1914#define ADC_TR2_HT2 ADC_TR2_HT2_Msk
1916/******************** Bit definition for ADC_TR3 register *******************/
1917#define ADC_TR3_LT3_Pos (0U)
1918#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)
1919#define ADC_TR3_LT3 ADC_TR3_LT3_Msk
1921#define ADC_TR3_HT3_Pos (16U)
1922#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)
1923#define ADC_TR3_HT3 ADC_TR3_HT3_Msk
1925/******************** Bit definition for ADC_SQR1 register ******************/
1926#define ADC_SQR1_L_Pos (0U)
1927#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1928#define ADC_SQR1_L ADC_SQR1_L_Msk
1929#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1930#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1931#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1932#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1934#define ADC_SQR1_SQ1_Pos (6U)
1935#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
1936#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
1937#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
1938#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
1939#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
1940#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
1941#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
1943#define ADC_SQR1_SQ2_Pos (12U)
1944#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
1945#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
1946#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
1947#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
1948#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
1949#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
1950#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
1952#define ADC_SQR1_SQ3_Pos (18U)
1953#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
1954#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
1955#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
1956#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
1957#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
1958#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
1959#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos)
1961#define ADC_SQR1_SQ4_Pos (24U)
1962#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
1963#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
1964#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
1965#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
1966#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
1967#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
1968#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
1970/******************** Bit definition for ADC_SQR2 register ******************/
1971#define ADC_SQR2_SQ5_Pos (0U)
1972#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
1973#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
1974#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
1975#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
1976#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
1977#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
1978#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
1980#define ADC_SQR2_SQ6_Pos (6U)
1981#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
1982#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
1983#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
1984#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
1985#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
1986#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
1987#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
1989#define ADC_SQR2_SQ7_Pos (12U)
1990#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1991#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1992#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1993#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1994#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1995#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1996#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1998#define ADC_SQR2_SQ8_Pos (18U)
1999#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
2000#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
2001#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
2002#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
2003#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
2004#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
2005#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
2007#define ADC_SQR2_SQ9_Pos (24U)
2008#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
2009#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
2010#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
2011#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
2012#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
2013#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
2014#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
2016/******************** Bit definition for ADC_SQR3 register ******************/
2017#define ADC_SQR3_SQ10_Pos (0U)
2018#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
2019#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
2020#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
2021#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
2022#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
2023#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
2024#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
2026#define ADC_SQR3_SQ11_Pos (6U)
2027#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
2028#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
2029#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
2030#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
2031#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
2032#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
2033#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
2035#define ADC_SQR3_SQ12_Pos (12U)
2036#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
2037#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
2038#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
2039#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
2040#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
2041#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
2042#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
2044#define ADC_SQR3_SQ13_Pos (18U)
2045#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
2046#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
2047#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
2048#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
2049#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
2050#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
2051#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
2053#define ADC_SQR3_SQ14_Pos (24U)
2054#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
2055#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
2056#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
2057#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
2058#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
2059#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
2060#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
2062/******************** Bit definition for ADC_SQR4 register ******************/
2063#define ADC_SQR4_SQ15_Pos (0U)
2064#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
2065#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
2066#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
2067#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
2068#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
2069#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
2070#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
2072#define ADC_SQR4_SQ16_Pos (6U)
2073#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
2074#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
2075#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
2076#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
2077#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
2078#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
2079#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
2081/******************** Bit definition for ADC_DR register ********************/
2082#define ADC_DR_RDATA_Pos (0U)
2083#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)
2084#define ADC_DR_RDATA ADC_DR_RDATA_Msk
2086/******************** Bit definition for ADC_JSQR register ******************/
2087#define ADC_JSQR_JL_Pos (0U)
2088#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
2089#define ADC_JSQR_JL ADC_JSQR_JL_Msk
2090#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
2091#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
2093#define ADC_JSQR_JEXTSEL_Pos (2U)
2094#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)
2095#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
2096#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)
2097#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)
2098#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)
2099#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)
2100#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)
2102#define ADC_JSQR_JEXTEN_Pos (7U)
2103#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
2104#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
2105#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
2106#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
2108#define ADC_JSQR_JSQ1_Pos (9U)
2109#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
2110#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
2111#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
2112#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
2113#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
2114#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
2115#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
2117#define ADC_JSQR_JSQ2_Pos (15U)
2118#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
2119#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
2120#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
2121#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
2122#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
2123#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
2124#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
2126#define ADC_JSQR_JSQ3_Pos (21U)
2127#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
2128#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
2129#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
2130#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
2131#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
2132#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
2133#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
2135#define ADC_JSQR_JSQ4_Pos (27U)
2136#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
2137#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
2138#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
2139#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
2140#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
2141#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
2142#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
2144/******************** Bit definition for ADC_OFR1 register ******************/
2145#define ADC_OFR1_OFFSET1_Pos (0U)
2146#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)
2147#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
2149#define ADC_OFR1_OFFSETPOS_Pos (24U)
2150#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos)
2151#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk
2152#define ADC_OFR1_SATEN_Pos (25U)
2153#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos)
2154#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk
2156#define ADC_OFR1_OFFSET1_CH_Pos (26U)
2157#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
2158#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
2159#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
2160#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
2161#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
2162#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
2163#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
2165#define ADC_OFR1_OFFSET1_EN_Pos (31U)
2166#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)
2167#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk
2169/******************** Bit definition for ADC_OFR2 register ******************/
2170#define ADC_OFR2_OFFSET2_Pos (0U)
2171#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)
2172#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
2174#define ADC_OFR2_OFFSETPOS_Pos (24U)
2175#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos)
2176#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk
2177#define ADC_OFR2_SATEN_Pos (25U)
2178#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos)
2179#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk
2181#define ADC_OFR2_OFFSET2_CH_Pos (26U)
2182#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
2183#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
2184#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
2185#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
2186#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
2187#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
2188#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
2190#define ADC_OFR2_OFFSET2_EN_Pos (31U)
2191#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)
2192#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk
2194/******************** Bit definition for ADC_OFR3 register ******************/
2195#define ADC_OFR3_OFFSET3_Pos (0U)
2196#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)
2197#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
2199#define ADC_OFR3_OFFSETPOS_Pos (24U)
2200#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos)
2201#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk
2202#define ADC_OFR3_SATEN_Pos (25U)
2203#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos)
2204#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk
2206#define ADC_OFR3_OFFSET3_CH_Pos (26U)
2207#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
2208#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
2209#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
2210#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
2211#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
2212#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
2213#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
2215#define ADC_OFR3_OFFSET3_EN_Pos (31U)
2216#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)
2217#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk
2219/******************** Bit definition for ADC_OFR4 register ******************/
2220#define ADC_OFR4_OFFSET4_Pos (0U)
2221#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)
2222#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
2224#define ADC_OFR4_OFFSETPOS_Pos (24U)
2225#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos)
2226#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk
2227#define ADC_OFR4_SATEN_Pos (25U)
2228#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos)
2229#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk
2231#define ADC_OFR4_OFFSET4_CH_Pos (26U)
2232#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
2233#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
2234#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
2235#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
2236#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
2237#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
2238#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
2240#define ADC_OFR4_OFFSET4_EN_Pos (31U)
2241#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)
2242#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk
2244/******************** Bit definition for ADC_JDR1 register ******************/
2245#define ADC_JDR1_JDATA_Pos (0U)
2246#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
2247#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
2249/******************** Bit definition for ADC_JDR2 register ******************/
2250#define ADC_JDR2_JDATA_Pos (0U)
2251#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
2252#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
2254/******************** Bit definition for ADC_JDR3 register ******************/
2255#define ADC_JDR3_JDATA_Pos (0U)
2256#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
2257#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
2259/******************** Bit definition for ADC_JDR4 register ******************/
2260#define ADC_JDR4_JDATA_Pos (0U)
2261#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
2262#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
2264/******************** Bit definition for ADC_AWD2CR register ****************/
2265#define ADC_AWD2CR_AWD2CH_Pos (0U)
2266#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)
2267#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
2268#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
2269#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
2270#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
2271#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
2272#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
2273#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
2274#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
2275#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
2276#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
2277#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
2278#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
2279#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
2280#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
2281#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
2282#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
2283#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
2284#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
2285#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
2286#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
2288/******************** Bit definition for ADC_AWD3CR register ****************/
2289#define ADC_AWD3CR_AWD3CH_Pos (0U)
2290#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)
2291#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
2292#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
2293#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
2294#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
2295#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
2296#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
2297#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
2298#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
2299#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
2300#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
2301#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
2302#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
2303#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
2304#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
2305#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
2306#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
2307#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
2308#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
2309#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
2310#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
2312/******************** Bit definition for ADC_DIFSEL register ****************/
2313#define ADC_DIFSEL_DIFSEL_Pos (0U)
2314#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)
2315#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
2316#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
2317#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
2318#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
2319#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
2320#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
2321#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
2322#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
2323#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
2324#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
2325#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
2326#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
2327#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
2328#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
2329#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
2330#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
2331#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
2332#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
2333#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
2334#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
2336/******************** Bit definition for ADC_CALFACT register ***************/
2337#define ADC_CALFACT_CALFACT_S_Pos (0U)
2338#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)
2339#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
2340#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)
2341#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)
2342#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)
2343#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)
2344#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)
2345#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)
2346#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)
2348#define ADC_CALFACT_CALFACT_D_Pos (16U)
2349#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)
2350#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
2351#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)
2352#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)
2353#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)
2354#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)
2355#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)
2356#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)
2357#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)
2359/******************** Bit definition for ADC_GCOMP register *****************/
2360#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
2361#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)
2362#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk
2364/************************* ADC Common registers *****************************/
2365/******************** Bit definition for ADC_CSR register *******************/
2366#define ADC_CSR_ADRDY_MST_Pos (0U)
2367#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
2368#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
2369#define ADC_CSR_EOSMP_MST_Pos (1U)
2370#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
2371#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
2372#define ADC_CSR_EOC_MST_Pos (2U)
2373#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
2374#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
2375#define ADC_CSR_EOS_MST_Pos (3U)
2376#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
2377#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
2378#define ADC_CSR_OVR_MST_Pos (4U)
2379#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
2380#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
2381#define ADC_CSR_JEOC_MST_Pos (5U)
2382#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
2383#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
2384#define ADC_CSR_JEOS_MST_Pos (6U)
2385#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
2386#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
2387#define ADC_CSR_AWD1_MST_Pos (7U)
2388#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
2389#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
2390#define ADC_CSR_AWD2_MST_Pos (8U)
2391#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
2392#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
2393#define ADC_CSR_AWD3_MST_Pos (9U)
2394#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
2395#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
2396#define ADC_CSR_JQOVF_MST_Pos (10U)
2397#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
2398#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
2400#define ADC_CSR_ADRDY_SLV_Pos (16U)
2401#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
2402#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
2403#define ADC_CSR_EOSMP_SLV_Pos (17U)
2404#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
2405#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
2406#define ADC_CSR_EOC_SLV_Pos (18U)
2407#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
2408#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
2409#define ADC_CSR_EOS_SLV_Pos (19U)
2410#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
2411#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
2412#define ADC_CSR_OVR_SLV_Pos (20U)
2413#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
2414#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
2415#define ADC_CSR_JEOC_SLV_Pos (21U)
2416#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
2417#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
2418#define ADC_CSR_JEOS_SLV_Pos (22U)
2419#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
2420#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
2421#define ADC_CSR_AWD1_SLV_Pos (23U)
2422#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
2423#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
2424#define ADC_CSR_AWD2_SLV_Pos (24U)
2425#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
2426#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
2427#define ADC_CSR_AWD3_SLV_Pos (25U)
2428#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
2429#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
2430#define ADC_CSR_JQOVF_SLV_Pos (26U)
2431#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
2432#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
2434/******************** Bit definition for ADC_CCR register *******************/
2435#define ADC_CCR_DUAL_Pos (0U)
2436#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
2437#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
2438#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
2439#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
2440#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
2441#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
2442#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
2444#define ADC_CCR_DELAY_Pos (8U)
2445#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
2446#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
2447#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
2448#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
2449#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
2450#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
2452#define ADC_CCR_DMACFG_Pos (13U)
2453#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)
2454#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk
2456#define ADC_CCR_MDMA_Pos (14U)
2457#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)
2458#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk
2459#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)
2460#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)
2462#define ADC_CCR_CKMODE_Pos (16U)
2463#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
2464#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
2465#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
2466#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
2468#define ADC_CCR_PRESC_Pos (18U)
2469#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
2470#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
2471#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
2472#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
2473#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
2474#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
2476#define ADC_CCR_VREFEN_Pos (22U)
2477#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
2478#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
2479#define ADC_CCR_VSENSESEL_Pos (23U)
2480#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos)
2481#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk
2482#define ADC_CCR_VBATSEL_Pos (24U)
2483#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos)
2484#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk
2486/******************** Bit definition for ADC_CDR register *******************/
2487#define ADC_CDR_RDATA_MST_Pos (0U)
2488#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
2489#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
2491#define ADC_CDR_RDATA_SLV_Pos (16U)
2492#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
2493#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
2496/******************************************************************************/
2497/* */
2498/* Analog Comparators (COMP) */
2499/* */
2500/******************************************************************************/
2501/********************** Bit definition for COMP_CSR register ****************/
2502#define COMP_CSR_EN_Pos (0U)
2503#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos)
2504#define COMP_CSR_EN COMP_CSR_EN_Msk
2506#define COMP_CSR_INMSEL_Pos (4U)
2507#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos)
2508#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk
2509#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos)
2510#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos)
2511#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos)
2512#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos)
2514#define COMP_CSR_INPSEL_Pos (8U)
2515#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos)
2516#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk
2518#define COMP_CSR_POLARITY_Pos (15U)
2519#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos)
2520#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk
2522#define COMP_CSR_HYST_Pos (16U)
2523#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos)
2524#define COMP_CSR_HYST COMP_CSR_HYST_Msk
2525#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos)
2526#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos)
2527#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos)
2529#define COMP_CSR_BLANKING_Pos (19U)
2530#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos)
2531#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk
2532#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos)
2533#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos)
2534#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos)
2536#define COMP_CSR_BRGEN_Pos (22U)
2537#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos)
2538#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk
2540#define COMP_CSR_SCALEN_Pos (23U)
2541#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos)
2542#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk
2544#define COMP_CSR_VALUE_Pos (30U)
2545#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos)
2546#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk
2548#define COMP_CSR_LOCK_Pos (31U)
2549#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos)
2550#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk
2552/******************************************************************************/
2553/* */
2554/* CORDIC calculation unit */
2555/* */
2556/******************************************************************************/
2557/******************* Bit definition for CORDIC_CSR register *****************/
2558#define CORDIC_CSR_FUNC_Pos (0U)
2559#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos)
2560#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk
2561#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos)
2562#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos)
2563#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos)
2564#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos)
2565#define CORDIC_CSR_PRECISION_Pos (4U)
2566#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)
2567#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk
2568#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos)
2569#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos)
2570#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos)
2571#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos)
2572#define CORDIC_CSR_SCALE_Pos (8U)
2573#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos)
2574#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk
2575#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos)
2576#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos)
2577#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos)
2578#define CORDIC_CSR_IEN_Pos (16U)
2579#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos)
2580#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk
2581#define CORDIC_CSR_DMAREN_Pos (17U)
2582#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos)
2583#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk
2584#define CORDIC_CSR_DMAWEN_Pos (18U)
2585#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos)
2586#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk
2587#define CORDIC_CSR_NRES_Pos (19U)
2588#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos)
2589#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk
2590#define CORDIC_CSR_NARGS_Pos (20U)
2591#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos)
2592#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk
2593#define CORDIC_CSR_RESSIZE_Pos (21U)
2594#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos)
2595#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk
2596#define CORDIC_CSR_ARGSIZE_Pos (22U)
2597#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos)
2598#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk
2599#define CORDIC_CSR_RRDY_Pos (31U)
2600#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos)
2601#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk
2603/******************* Bit definition for CORDIC_WDATA register ***************/
2604#define CORDIC_WDATA_ARG_Pos (0U)
2605#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)
2606#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk
2608/******************* Bit definition for CORDIC_RDATA register ***************/
2609#define CORDIC_RDATA_RES_Pos (0U)
2610#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)
2611#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk
2613/******************************************************************************/
2614/* */
2615/* CRC calculation unit */
2616/* */
2617/******************************************************************************/
2618/******************* Bit definition for CRC_DR register *********************/
2619#define CRC_DR_DR_Pos (0U)
2620#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
2621#define CRC_DR_DR CRC_DR_DR_Msk
2623/******************* Bit definition for CRC_IDR register ********************/
2624#define CRC_IDR_IDR_Pos (0U)
2625#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)
2626#define CRC_IDR_IDR CRC_IDR_IDR_Msk
2628/******************** Bit definition for CRC_CR register ********************/
2629#define CRC_CR_RESET_Pos (0U)
2630#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
2631#define CRC_CR_RESET CRC_CR_RESET_Msk
2632#define CRC_CR_POLYSIZE_Pos (3U)
2633#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
2634#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
2635#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
2636#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
2637#define CRC_CR_REV_IN_Pos (5U)
2638#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
2639#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
2640#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
2641#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
2642#define CRC_CR_REV_OUT_Pos (7U)
2643#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
2644#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
2646/******************* Bit definition for CRC_INIT register *******************/
2647#define CRC_INIT_INIT_Pos (0U)
2648#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
2649#define CRC_INIT_INIT CRC_INIT_INIT_Msk
2651/******************* Bit definition for CRC_POL register ********************/
2652#define CRC_POL_POL_Pos (0U)
2653#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
2654#define CRC_POL_POL CRC_POL_POL_Msk
2656/******************************************************************************/
2657/* */
2658/* CRS Clock Recovery System */
2659/******************************************************************************/
2660
2661/******************* Bit definition for CRS_CR register *********************/
2662#define CRS_CR_SYNCOKIE_Pos (0U)
2663#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
2664#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
2665#define CRS_CR_SYNCWARNIE_Pos (1U)
2666#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
2667#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
2668#define CRS_CR_ERRIE_Pos (2U)
2669#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
2670#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
2671#define CRS_CR_ESYNCIE_Pos (3U)
2672#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
2673#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
2674#define CRS_CR_CEN_Pos (5U)
2675#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
2676#define CRS_CR_CEN CRS_CR_CEN_Msk
2677#define CRS_CR_AUTOTRIMEN_Pos (6U)
2678#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
2679#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
2680#define CRS_CR_SWSYNC_Pos (7U)
2681#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
2682#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
2683#define CRS_CR_TRIM_Pos (8U)
2684#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos)
2685#define CRS_CR_TRIM CRS_CR_TRIM_Msk
2687/******************* Bit definition for CRS_CFGR register *********************/
2688#define CRS_CFGR_RELOAD_Pos (0U)
2689#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
2690#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
2691#define CRS_CFGR_FELIM_Pos (16U)
2692#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
2693#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
2695#define CRS_CFGR_SYNCDIV_Pos (24U)
2696#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
2697#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
2698#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
2699#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
2700#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
2702#define CRS_CFGR_SYNCSRC_Pos (28U)
2703#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
2704#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
2705#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
2706#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
2708#define CRS_CFGR_SYNCPOL_Pos (31U)
2709#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
2710#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
2712/******************* Bit definition for CRS_ISR register *********************/
2713#define CRS_ISR_SYNCOKF_Pos (0U)
2714#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
2715#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
2716#define CRS_ISR_SYNCWARNF_Pos (1U)
2717#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
2718#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
2719#define CRS_ISR_ERRF_Pos (2U)
2720#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
2721#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
2722#define CRS_ISR_ESYNCF_Pos (3U)
2723#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
2724#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
2725#define CRS_ISR_SYNCERR_Pos (8U)
2726#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
2727#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
2728#define CRS_ISR_SYNCMISS_Pos (9U)
2729#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
2730#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
2731#define CRS_ISR_TRIMOVF_Pos (10U)
2732#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
2733#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
2734#define CRS_ISR_FEDIR_Pos (15U)
2735#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
2736#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
2737#define CRS_ISR_FECAP_Pos (16U)
2738#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
2739#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
2741/******************* Bit definition for CRS_ICR register *********************/
2742#define CRS_ICR_SYNCOKC_Pos (0U)
2743#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
2744#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
2745#define CRS_ICR_SYNCWARNC_Pos (1U)
2746#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
2747#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
2748#define CRS_ICR_ERRC_Pos (2U)
2749#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
2750#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
2751#define CRS_ICR_ESYNCC_Pos (3U)
2752#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
2753#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
2755/******************************************************************************/
2756/* */
2757/* Digital to Analog Converter */
2758/* */
2759/******************************************************************************/
2760/*
2761 * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
2762 */
2763#define DAC_CHANNEL2_SUPPORT
2765/******************** Bit definition for DAC_CR register ********************/
2766#define DAC_CR_EN1_Pos (0U)
2767#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
2768#define DAC_CR_EN1 DAC_CR_EN1_Msk
2769#define DAC_CR_TEN1_Pos (1U)
2770#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
2771#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
2773#define DAC_CR_TSEL1_Pos (2U)
2774#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)
2775#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
2776#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
2777#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
2778#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
2779#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)
2781#define DAC_CR_WAVE1_Pos (6U)
2782#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
2783#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
2784#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
2785#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
2787#define DAC_CR_MAMP1_Pos (8U)
2788#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
2789#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
2790#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
2791#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
2792#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
2793#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
2795#define DAC_CR_DMAEN1_Pos (12U)
2796#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
2797#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
2798#define DAC_CR_DMAUDRIE1_Pos (13U)
2799#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
2800#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
2801#define DAC_CR_CEN1_Pos (14U)
2802#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
2803#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
2805#define DAC_CR_HFSEL_Pos (15U)
2806#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos)
2807#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk
2809#define DAC_CR_EN2_Pos (16U)
2810#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
2811#define DAC_CR_EN2 DAC_CR_EN2_Msk
2812#define DAC_CR_TEN2_Pos (17U)
2813#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
2814#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
2816#define DAC_CR_TSEL2_Pos (18U)
2817#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)
2818#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
2819#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
2820#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
2821#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
2822#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)
2824#define DAC_CR_WAVE2_Pos (22U)
2825#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
2826#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
2827#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
2828#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
2830#define DAC_CR_MAMP2_Pos (24U)
2831#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
2832#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
2833#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
2834#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
2835#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
2836#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
2838#define DAC_CR_DMAEN2_Pos (28U)
2839#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
2840#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
2841#define DAC_CR_DMAUDRIE2_Pos (29U)
2842#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
2843#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
2844#define DAC_CR_CEN2_Pos (30U)
2845#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
2846#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
2848/***************** Bit definition for DAC_SWTRIGR register ******************/
2849#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
2850#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
2851#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
2852#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
2853#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
2854#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
2855#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
2856#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)
2857#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk
2858#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
2859#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)
2860#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk
2862/***************** Bit definition for DAC_DHR12R1 register ******************/
2863#define DAC_DHR12R1_DACC1DHR_Pos (0U)
2864#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
2865#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
2866#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
2867#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)
2868#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk
2870/***************** Bit definition for DAC_DHR12L1 register ******************/
2871#define DAC_DHR12L1_DACC1DHR_Pos (4U)
2872#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
2873#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
2874#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
2875#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)
2876#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk
2878/****************** Bit definition for DAC_DHR8R1 register ******************/
2879#define DAC_DHR8R1_DACC1DHR_Pos (0U)
2880#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
2881#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
2882#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
2883#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)
2884#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk
2886/***************** Bit definition for DAC_DHR12R2 register ******************/
2887#define DAC_DHR12R2_DACC2DHR_Pos (0U)
2888#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
2889#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
2890#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
2891#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)
2892#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk
2894/***************** Bit definition for DAC_DHR12L2 register ******************/
2895#define DAC_DHR12L2_DACC2DHR_Pos (4U)
2896#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
2897#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
2898#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
2899#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)
2900#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk
2902/****************** Bit definition for DAC_DHR8R2 register ******************/
2903#define DAC_DHR8R2_DACC2DHR_Pos (0U)
2904#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
2905#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
2906#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
2907#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)
2908#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk
2910/***************** Bit definition for DAC_DHR12RD register ******************/
2911#define DAC_DHR12RD_DACC1DHR_Pos (0U)
2912#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
2913#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
2914#define DAC_DHR12RD_DACC2DHR_Pos (16U)
2915#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
2916#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
2918/***************** Bit definition for DAC_DHR12LD register ******************/
2919#define DAC_DHR12LD_DACC1DHR_Pos (4U)
2920#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
2921#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
2922#define DAC_DHR12LD_DACC2DHR_Pos (20U)
2923#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
2924#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
2926/****************** Bit definition for DAC_DHR8RD register ******************/
2927#define DAC_DHR8RD_DACC1DHR_Pos (0U)
2928#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
2929#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
2930#define DAC_DHR8RD_DACC2DHR_Pos (8U)
2931#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
2932#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
2934/******************* Bit definition for DAC_DOR1 register *******************/
2935#define DAC_DOR1_DACC1DOR_Pos (0U)
2936#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
2937#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
2938#define DAC_DOR1_DACC1DORB_Pos (16U)
2939#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)
2940#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk
2942/******************* Bit definition for DAC_DOR2 register *******************/
2943#define DAC_DOR2_DACC2DOR_Pos (0U)
2944#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
2945#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
2946#define DAC_DOR2_DACC2DORB_Pos (16U)
2947#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)
2948#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk
2950/******************** Bit definition for DAC_SR register ********************/
2951#define DAC_SR_DAC1RDY_Pos (11U)
2952#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos)
2953#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk
2954#define DAC_SR_DORSTAT1_Pos (12U)
2955#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos)
2956#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk
2957#define DAC_SR_DMAUDR1_Pos (13U)
2958#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
2959#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
2960#define DAC_SR_CAL_FLAG1_Pos (14U)
2961#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
2962#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
2963#define DAC_SR_BWST1_Pos (15U)
2964#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos)
2965#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
2967#define DAC_SR_DAC2RDY_Pos (27U)
2968#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos)
2969#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk
2970#define DAC_SR_DORSTAT2_Pos (28U)
2971#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos)
2972#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk
2973#define DAC_SR_DMAUDR2_Pos (29U)
2974#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
2975#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
2976#define DAC_SR_CAL_FLAG2_Pos (30U)
2977#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
2978#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
2979#define DAC_SR_BWST2_Pos (31U)
2980#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
2981#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
2983/******************* Bit definition for DAC_CCR register ********************/
2984#define DAC_CCR_OTRIM1_Pos (0U)
2985#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
2986#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
2987#define DAC_CCR_OTRIM2_Pos (16U)
2988#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
2989#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
2991/******************* Bit definition for DAC_MCR register *******************/
2992#define DAC_MCR_MODE1_Pos (0U)
2993#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
2994#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
2995#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
2996#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
2997#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
2999#define DAC_MCR_DMADOUBLE1_Pos (8U)
3000#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos)
3001#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk
3003#define DAC_MCR_SINFORMAT1_Pos (9U)
3004#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos)
3005#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk
3007#define DAC_MCR_HFSEL_Pos (14U)
3008#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos)
3009#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk
3010#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos)
3011#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos)
3013#define DAC_MCR_MODE2_Pos (16U)
3014#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
3015#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
3016#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
3017#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
3018#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
3020#define DAC_MCR_DMADOUBLE2_Pos (24U)
3021#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos)
3022#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk
3024#define DAC_MCR_SINFORMAT2_Pos (25U)
3025#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos)
3026#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk
3028/****************** Bit definition for DAC_SHSR1 register ******************/
3029#define DAC_SHSR1_TSAMPLE1_Pos (0U)
3030#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
3031#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
3033/****************** Bit definition for DAC_SHSR2 register ******************/
3034#define DAC_SHSR2_TSAMPLE2_Pos (0U)
3035#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
3036#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
3038/****************** Bit definition for DAC_SHHR register ******************/
3039#define DAC_SHHR_THOLD1_Pos (0U)
3040#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
3041#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
3042#define DAC_SHHR_THOLD2_Pos (16U)
3043#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
3044#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
3046/****************** Bit definition for DAC_SHRR register ******************/
3047#define DAC_SHRR_TREFRESH1_Pos (0U)
3048#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
3049#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
3050#define DAC_SHRR_TREFRESH2_Pos (16U)
3051#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
3052#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
3054/****************** Bit definition for DAC_STR1 register ******************/
3055#define DAC_STR1_STRSTDATA1_Pos (0U)
3056#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)
3057#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk
3058#define DAC_STR1_STDIR1_Pos (12U)
3059#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos)
3060#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk
3062#define DAC_STR1_STINCDATA1_Pos (16U)
3063#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)
3064#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk
3066/****************** Bit definition for DAC_STR2 register ******************/
3067#define DAC_STR2_STRSTDATA2_Pos (0U)
3068#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)
3069#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk
3070#define DAC_STR2_STDIR2_Pos (12U)
3071#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos)
3072#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk
3074#define DAC_STR2_STINCDATA2_Pos (16U)
3075#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)
3076#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk
3078/****************** Bit definition for DAC_STMODR register ****************/
3079#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
3080#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)
3081#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk
3082#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)
3083#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)
3084#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)
3085#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)
3087#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
3088#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)
3089#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk
3090#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)
3091#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)
3092#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)
3093#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)
3095#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
3096#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)
3097#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk
3098#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)
3099#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)
3100#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)
3101#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)
3103#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
3104#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)
3105#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk
3106#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)
3107#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)
3108#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)
3109#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)
3111/******************************************************************************/
3112/* */
3113/* Debug MCU */
3114/* */
3115/******************************************************************************/
3116/******************** Bit definition for DBGMCU_IDCODE register *************/
3117#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
3118#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
3119#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
3120#define DBGMCU_IDCODE_REV_ID_Pos (16U)
3121#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
3122#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
3123
3124/******************** Bit definition for DBGMCU_CR register *****************/
3125#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
3126#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
3127#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
3128#define DBGMCU_CR_DBG_STOP_Pos (1U)
3129#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
3130#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
3131#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
3132#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
3133#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
3134#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
3135#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
3136#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
3137
3138#define DBGMCU_CR_TRACE_MODE_Pos (6U)
3139#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
3140#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
3141#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
3142#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
3144/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
3145#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
3146#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
3147#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
3148#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
3149#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
3150#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
3151#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
3152#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)
3153#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
3154#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
3155#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
3156#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
3157#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
3158#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
3159#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
3160#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
3161#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
3162#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
3163#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
3164#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)
3165#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
3166#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
3167#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
3168#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
3169#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
3170#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
3171#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
3172#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
3173#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
3174#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
3175#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
3176#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
3177#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
3178#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
3179#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)
3180#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
3181#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
3182#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)
3183#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
3184
3185/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
3186#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
3187#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)
3188#define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
3189
3190/******************** Bit definition for DBGMCU_APB2FZ register ************/
3191#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
3192#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)
3193#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
3194#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
3195#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)
3196#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
3197#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
3198#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)
3199#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
3200#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
3201#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)
3202#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
3203#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
3204#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)
3205#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
3206#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
3207#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)
3208#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
3209#define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos (26U)
3210#define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos)
3211#define DBGMCU_APB2FZ_DBG_HRTIM1_STOP DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk
3212
3213/******************************************************************************/
3214/* */
3215/* DMA Controller (DMA) */
3216/* */
3217/******************************************************************************/
3218
3219/******************* Bit definition for DMA_ISR register ********************/
3220#define DMA_ISR_GIF1_Pos (0U)
3221#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
3222#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
3223#define DMA_ISR_TCIF1_Pos (1U)
3224#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
3225#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
3226#define DMA_ISR_HTIF1_Pos (2U)
3227#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
3228#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
3229#define DMA_ISR_TEIF1_Pos (3U)
3230#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
3231#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
3232#define DMA_ISR_GIF2_Pos (4U)
3233#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
3234#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
3235#define DMA_ISR_TCIF2_Pos (5U)
3236#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
3237#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
3238#define DMA_ISR_HTIF2_Pos (6U)
3239#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
3240#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
3241#define DMA_ISR_TEIF2_Pos (7U)
3242#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
3243#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
3244#define DMA_ISR_GIF3_Pos (8U)
3245#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
3246#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
3247#define DMA_ISR_TCIF3_Pos (9U)
3248#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
3249#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
3250#define DMA_ISR_HTIF3_Pos (10U)
3251#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
3252#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
3253#define DMA_ISR_TEIF3_Pos (11U)
3254#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
3255#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
3256#define DMA_ISR_GIF4_Pos (12U)
3257#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
3258#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
3259#define DMA_ISR_TCIF4_Pos (13U)
3260#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
3261#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
3262#define DMA_ISR_HTIF4_Pos (14U)
3263#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
3264#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
3265#define DMA_ISR_TEIF4_Pos (15U)
3266#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
3267#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
3268#define DMA_ISR_GIF5_Pos (16U)
3269#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
3270#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
3271#define DMA_ISR_TCIF5_Pos (17U)
3272#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
3273#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
3274#define DMA_ISR_HTIF5_Pos (18U)
3275#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
3276#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
3277#define DMA_ISR_TEIF5_Pos (19U)
3278#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
3279#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
3280#define DMA_ISR_GIF6_Pos (20U)
3281#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
3282#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
3283#define DMA_ISR_TCIF6_Pos (21U)
3284#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
3285#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
3286#define DMA_ISR_HTIF6_Pos (22U)
3287#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
3288#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
3289#define DMA_ISR_TEIF6_Pos (23U)
3290#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
3291#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
3292#define DMA_ISR_GIF7_Pos (24U)
3293#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
3294#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
3295#define DMA_ISR_TCIF7_Pos (25U)
3296#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
3297#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
3298#define DMA_ISR_HTIF7_Pos (26U)
3299#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
3300#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
3301#define DMA_ISR_TEIF7_Pos (27U)
3302#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
3303#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
3304#define DMA_ISR_GIF8_Pos (28U)
3305#define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos)
3306#define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk
3307#define DMA_ISR_TCIF8_Pos (29U)
3308#define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos)
3309#define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk
3310#define DMA_ISR_HTIF8_Pos (30U)
3311#define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos)
3312#define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk
3313#define DMA_ISR_TEIF8_Pos (31U)
3314#define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos)
3315#define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk
3317/******************* Bit definition for DMA_IFCR register *******************/
3318#define DMA_IFCR_CGIF1_Pos (0U)
3319#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
3320#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
3321#define DMA_IFCR_CTCIF1_Pos (1U)
3322#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
3323#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
3324#define DMA_IFCR_CHTIF1_Pos (2U)
3325#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
3326#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
3327#define DMA_IFCR_CTEIF1_Pos (3U)
3328#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
3329#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
3330#define DMA_IFCR_CGIF2_Pos (4U)
3331#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
3332#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
3333#define DMA_IFCR_CTCIF2_Pos (5U)
3334#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
3335#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
3336#define DMA_IFCR_CHTIF2_Pos (6U)
3337#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
3338#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
3339#define DMA_IFCR_CTEIF2_Pos (7U)
3340#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
3341#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
3342#define DMA_IFCR_CGIF3_Pos (8U)
3343#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
3344#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
3345#define DMA_IFCR_CTCIF3_Pos (9U)
3346#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
3347#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
3348#define DMA_IFCR_CHTIF3_Pos (10U)
3349#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
3350#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
3351#define DMA_IFCR_CTEIF3_Pos (11U)
3352#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
3353#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
3354#define DMA_IFCR_CGIF4_Pos (12U)
3355#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
3356#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
3357#define DMA_IFCR_CTCIF4_Pos (13U)
3358#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
3359#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
3360#define DMA_IFCR_CHTIF4_Pos (14U)
3361#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
3362#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
3363#define DMA_IFCR_CTEIF4_Pos (15U)
3364#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
3365#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
3366#define DMA_IFCR_CGIF5_Pos (16U)
3367#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
3368#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
3369#define DMA_IFCR_CTCIF5_Pos (17U)
3370#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
3371#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
3372#define DMA_IFCR_CHTIF5_Pos (18U)
3373#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
3374#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
3375#define DMA_IFCR_CTEIF5_Pos (19U)
3376#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
3377#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
3378#define DMA_IFCR_CGIF6_Pos (20U)
3379#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
3380#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
3381#define DMA_IFCR_CTCIF6_Pos (21U)
3382#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
3383#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
3384#define DMA_IFCR_CHTIF6_Pos (22U)
3385#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
3386#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
3387#define DMA_IFCR_CTEIF6_Pos (23U)
3388#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
3389#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
3390#define DMA_IFCR_CGIF7_Pos (24U)
3391#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
3392#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
3393#define DMA_IFCR_CTCIF7_Pos (25U)
3394#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
3395#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
3396#define DMA_IFCR_CHTIF7_Pos (26U)
3397#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
3398#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
3399#define DMA_IFCR_CTEIF7_Pos (27U)
3400#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
3401#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
3402#define DMA_IFCR_CGIF8_Pos (28U)
3403#define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos)
3404#define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk
3405#define DMA_IFCR_CTCIF8_Pos (29U)
3406#define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos)
3407#define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk
3408#define DMA_IFCR_CHTIF8_Pos (30U)
3409#define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos)
3410#define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk
3411#define DMA_IFCR_CTEIF8_Pos (31U)
3412#define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos)
3413#define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk
3415/******************* Bit definition for DMA_CCR register ********************/
3416#define DMA_CCR_EN_Pos (0U)
3417#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
3418#define DMA_CCR_EN DMA_CCR_EN_Msk
3419#define DMA_CCR_TCIE_Pos (1U)
3420#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
3421#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
3422#define DMA_CCR_HTIE_Pos (2U)
3423#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
3424#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
3425#define DMA_CCR_TEIE_Pos (3U)
3426#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
3427#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
3428#define DMA_CCR_DIR_Pos (4U)
3429#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
3430#define DMA_CCR_DIR DMA_CCR_DIR_Msk
3431#define DMA_CCR_CIRC_Pos (5U)
3432#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
3433#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
3434#define DMA_CCR_PINC_Pos (6U)
3435#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
3436#define DMA_CCR_PINC DMA_CCR_PINC_Msk
3437#define DMA_CCR_MINC_Pos (7U)
3438#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
3439#define DMA_CCR_MINC DMA_CCR_MINC_Msk
3441#define DMA_CCR_PSIZE_Pos (8U)
3442#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
3443#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
3444#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
3445#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
3447#define DMA_CCR_MSIZE_Pos (10U)
3448#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
3449#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
3450#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
3451#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
3453#define DMA_CCR_PL_Pos (12U)
3454#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
3455#define DMA_CCR_PL DMA_CCR_PL_Msk
3456#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
3457#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
3459#define DMA_CCR_MEM2MEM_Pos (14U)
3460#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
3461#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
3463/****************** Bit definition for DMA_CNDTR register *******************/
3464#define DMA_CNDTR_NDT_Pos (0U)
3465#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
3466#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
3468/****************** Bit definition for DMA_CPAR register ********************/
3469#define DMA_CPAR_PA_Pos (0U)
3470#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
3471#define DMA_CPAR_PA DMA_CPAR_PA_Msk
3473/****************** Bit definition for DMA_CMAR register ********************/
3474#define DMA_CMAR_MA_Pos (0U)
3475#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
3476#define DMA_CMAR_MA DMA_CMAR_MA_Msk
3478/******************************************************************************/
3479/* */
3480/* DMAMUX Controller */
3481/* */
3482/******************************************************************************/
3483
3484/******************** Bits definition for DMAMUX_CxCR register **************/
3485#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
3486#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3487#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
3488#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3489#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3490#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3491#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3492#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3493#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3494#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3495#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
3497#define DMAMUX_CxCR_SOIE_Pos (8U)
3498#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)
3499#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
3500
3501#define DMAMUX_CxCR_EGE_Pos (9U)
3502#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)
3503#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
3504
3505#define DMAMUX_CxCR_SE_Pos (16U)
3506#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)
3507#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
3508
3509#define DMAMUX_CxCR_SPOL_Pos (17U)
3510#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)
3511#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
3512#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)
3513#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)
3515#define DMAMUX_CxCR_NBREQ_Pos (19U)
3516#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)
3517#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
3518#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)
3519#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)
3520#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)
3521#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)
3522#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)
3524#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
3525#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)
3526#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
3527#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)
3528#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)
3529#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)
3530#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)
3531#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)
3533/******************** Bits definition for DMAMUX_CSR register ****************/
3534#define DMAMUX_CSR_SOF0_Pos (0U)
3535#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)
3536#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
3537#define DMAMUX_CSR_SOF1_Pos (1U)
3538#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)
3539#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
3540#define DMAMUX_CSR_SOF2_Pos (2U)
3541#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)
3542#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
3543#define DMAMUX_CSR_SOF3_Pos (3U)
3544#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)
3545#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
3546#define DMAMUX_CSR_SOF4_Pos (4U)
3547#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)
3548#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
3549#define DMAMUX_CSR_SOF5_Pos (5U)
3550#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)
3551#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
3552#define DMAMUX_CSR_SOF6_Pos (6U)
3553#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)
3554#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
3555#define DMAMUX_CSR_SOF7_Pos (7U)
3556#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)
3557#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
3558#define DMAMUX_CSR_SOF8_Pos (8U)
3559#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)
3560#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
3561#define DMAMUX_CSR_SOF9_Pos (9U)
3562#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)
3563#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
3564#define DMAMUX_CSR_SOF10_Pos (10U)
3565#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)
3566#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
3567#define DMAMUX_CSR_SOF11_Pos (11U)
3568#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)
3569#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
3570#define DMAMUX_CSR_SOF12_Pos (12U)
3571#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)
3572#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
3573#define DMAMUX_CSR_SOF13_Pos (13U)
3574#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)
3575#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
3576#define DMAMUX_CSR_SOF14_Pos (14U)
3577#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)
3578#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
3579#define DMAMUX_CSR_SOF15_Pos (15U)
3580#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)
3581#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
3582
3583/******************** Bits definition for DMAMUX_CFR register ****************/
3584#define DMAMUX_CFR_CSOF0_Pos (0U)
3585#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)
3586#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
3587#define DMAMUX_CFR_CSOF1_Pos (1U)
3588#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)
3589#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
3590#define DMAMUX_CFR_CSOF2_Pos (2U)
3591#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)
3592#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
3593#define DMAMUX_CFR_CSOF3_Pos (3U)
3594#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)
3595#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
3596#define DMAMUX_CFR_CSOF4_Pos (4U)
3597#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)
3598#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
3599#define DMAMUX_CFR_CSOF5_Pos (5U)
3600#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)
3601#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
3602#define DMAMUX_CFR_CSOF6_Pos (6U)
3603#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)
3604#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
3605#define DMAMUX_CFR_CSOF7_Pos (7U)
3606#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)
3607#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
3608#define DMAMUX_CFR_CSOF8_Pos (8U)
3609#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)
3610#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
3611#define DMAMUX_CFR_CSOF9_Pos (9U)
3612#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)
3613#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
3614#define DMAMUX_CFR_CSOF10_Pos (10U)
3615#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)
3616#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
3617#define DMAMUX_CFR_CSOF11_Pos (11U)
3618#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)
3619#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
3620#define DMAMUX_CFR_CSOF12_Pos (12U)
3621#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)
3622#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
3623#define DMAMUX_CFR_CSOF13_Pos (13U)
3624#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)
3625#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
3626#define DMAMUX_CFR_CSOF14_Pos (14U)
3627#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)
3628#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
3629#define DMAMUX_CFR_CSOF15_Pos (15U)
3630#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)
3631#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
3632
3633/******************** Bits definition for DMAMUX_RGxCR register ************/
3634#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
3635#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)
3636#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
3637#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)
3638#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)
3639#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)
3640#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)
3641#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)
3643#define DMAMUX_RGxCR_OIE_Pos (8U)
3644#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)
3645#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
3646
3647#define DMAMUX_RGxCR_GE_Pos (16U)
3648#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)
3649#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
3650
3651#define DMAMUX_RGxCR_GPOL_Pos (17U)
3652#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)
3653#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
3654#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)
3655#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)
3657#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
3658#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)
3659#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
3660#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)
3661#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)
3662#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)
3663#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)
3664#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)
3666/******************** Bits definition for DMAMUX_RGSR register **************/
3667#define DMAMUX_RGSR_OF0_Pos (0U)
3668#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)
3669#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
3670#define DMAMUX_RGSR_OF1_Pos (1U)
3671#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)
3672#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
3673#define DMAMUX_RGSR_OF2_Pos (2U)
3674#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)
3675#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
3676#define DMAMUX_RGSR_OF3_Pos (3U)
3677#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)
3678#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
3679
3680/******************** Bits definition for DMAMUX_RGCFR register ************/
3681#define DMAMUX_RGCFR_COF0_Pos (0U)
3682#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)
3683#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
3684#define DMAMUX_RGCFR_COF1_Pos (1U)
3685#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)
3686#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
3687#define DMAMUX_RGCFR_COF2_Pos (2U)
3688#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)
3689#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
3690#define DMAMUX_RGCFR_COF3_Pos (3U)
3691#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)
3692#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
3693
3694/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
3695#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
3696#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)
3697#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3698#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
3699#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)
3700#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3701#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
3702#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)
3703#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3704#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
3705#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)
3706#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3707#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
3708#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)
3709#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3710#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
3711#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)
3712#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3713#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
3714#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)
3715#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3716#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
3717#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)
3718#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3719
3720/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
3721#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
3722#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)
3723#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3724#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
3725#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)
3726#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3727#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
3728#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)
3729#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3730#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
3731#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)
3732#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3733#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
3734#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)
3735#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3736#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
3737#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)
3738#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3739#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
3740#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)
3741#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3742#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
3743#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)
3744#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3745#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
3746#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)
3747#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3748#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
3749#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)
3750#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3751#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
3752#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)
3753#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3754#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
3755#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)
3756#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3757#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
3758#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)
3759#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3760#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
3761#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)
3762#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3763#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
3764#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)
3765#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3766#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
3767#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)
3768#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3769#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
3770#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)
3771#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3772#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
3773#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)
3774#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3775#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
3776#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)
3777#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3778#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
3779#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)
3780#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3781#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
3782#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)
3783#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3784#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
3785#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)
3786#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3787#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
3788#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)
3789#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3790#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
3791#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)
3792#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3793#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
3794#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)
3795#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3796#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
3797#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)
3798#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3799#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
3800#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)
3801#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3802#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
3803#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)
3804#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3805#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
3806#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)
3807#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3808#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
3809#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)
3810#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3811#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
3812#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)
3813#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3814#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
3815#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)
3816#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3817
3818
3819/******************************************************************************/
3820/* */
3821/* External Interrupt/Event Controller */
3822/* */
3823/******************************************************************************/
3824/******************* Bit definition for EXTI_IMR1 register ******************/
3825#define EXTI_IMR1_IM0_Pos (0U)
3826#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
3827#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
3828#define EXTI_IMR1_IM1_Pos (1U)
3829#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
3830#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
3831#define EXTI_IMR1_IM2_Pos (2U)
3832#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
3833#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
3834#define EXTI_IMR1_IM3_Pos (3U)
3835#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
3836#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
3837#define EXTI_IMR1_IM4_Pos (4U)
3838#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
3839#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
3840#define EXTI_IMR1_IM5_Pos (5U)
3841#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
3842#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
3843#define EXTI_IMR1_IM6_Pos (6U)
3844#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
3845#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
3846#define EXTI_IMR1_IM7_Pos (7U)
3847#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
3848#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
3849#define EXTI_IMR1_IM8_Pos (8U)
3850#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
3851#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
3852#define EXTI_IMR1_IM9_Pos (9U)
3853#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
3854#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
3855#define EXTI_IMR1_IM10_Pos (10U)
3856#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
3857#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
3858#define EXTI_IMR1_IM11_Pos (11U)
3859#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
3860#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
3861#define EXTI_IMR1_IM12_Pos (12U)
3862#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
3863#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
3864#define EXTI_IMR1_IM13_Pos (13U)
3865#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
3866#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
3867#define EXTI_IMR1_IM14_Pos (14U)
3868#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
3869#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
3870#define EXTI_IMR1_IM15_Pos (15U)
3871#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
3872#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
3873#define EXTI_IMR1_IM16_Pos (16U)
3874#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
3875#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
3876#define EXTI_IMR1_IM17_Pos (17U)
3877#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
3878#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
3879#define EXTI_IMR1_IM18_Pos (18U)
3880#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
3881#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
3882#define EXTI_IMR1_IM19_Pos (19U)
3883#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
3884#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
3885#define EXTI_IMR1_IM20_Pos (20U)
3886#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
3887#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
3888#define EXTI_IMR1_IM21_Pos (21U)
3889#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
3890#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
3891#define EXTI_IMR1_IM22_Pos (22U)
3892#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
3893#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
3894#define EXTI_IMR1_IM23_Pos (23U)
3895#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
3896#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
3897#define EXTI_IMR1_IM24_Pos (24U)
3898#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
3899#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
3900#define EXTI_IMR1_IM25_Pos (25U)
3901#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
3902#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
3903#define EXTI_IMR1_IM26_Pos (26U)
3904#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
3905#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
3906#define EXTI_IMR1_IM27_Pos (27U)
3907#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
3908#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
3909#define EXTI_IMR1_IM28_Pos (28U)
3910#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
3911#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
3912#define EXTI_IMR1_IM29_Pos (29U)
3913#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
3914#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
3915#define EXTI_IMR1_IM30_Pos (30U)
3916#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
3917#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
3918#define EXTI_IMR1_IM31_Pos (31U)
3919#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
3920#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
3921#define EXTI_IMR1_IM_Pos (0U)
3922#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
3923#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
3925/******************* Bit definition for EXTI_EMR1 register ******************/
3926#define EXTI_EMR1_EM0_Pos (0U)
3927#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
3928#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
3929#define EXTI_EMR1_EM1_Pos (1U)
3930#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
3931#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
3932#define EXTI_EMR1_EM2_Pos (2U)
3933#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
3934#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
3935#define EXTI_EMR1_EM3_Pos (3U)
3936#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
3937#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
3938#define EXTI_EMR1_EM4_Pos (4U)
3939#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
3940#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
3941#define EXTI_EMR1_EM5_Pos (5U)
3942#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
3943#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
3944#define EXTI_EMR1_EM6_Pos (6U)
3945#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
3946#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
3947#define EXTI_EMR1_EM7_Pos (7U)
3948#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
3949#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
3950#define EXTI_EMR1_EM8_Pos (8U)
3951#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
3952#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
3953#define EXTI_EMR1_EM9_Pos (9U)
3954#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
3955#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
3956#define EXTI_EMR1_EM10_Pos (10U)
3957#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
3958#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
3959#define EXTI_EMR1_EM11_Pos (11U)
3960#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
3961#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
3962#define EXTI_EMR1_EM12_Pos (12U)
3963#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
3964#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
3965#define EXTI_EMR1_EM13_Pos (13U)
3966#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
3967#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
3968#define EXTI_EMR1_EM14_Pos (14U)
3969#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
3970#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
3971#define EXTI_EMR1_EM15_Pos (15U)
3972#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
3973#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
3974#define EXTI_EMR1_EM16_Pos (16U)
3975#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
3976#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
3977#define EXTI_EMR1_EM17_Pos (17U)
3978#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
3979#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
3980#define EXTI_EMR1_EM18_Pos (18U)
3981#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
3982#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
3983#define EXTI_EMR1_EM19_Pos (19U)
3984#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)
3985#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk
3986#define EXTI_EMR1_EM20_Pos (20U)
3987#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
3988#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
3989#define EXTI_EMR1_EM21_Pos (21U)
3990#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
3991#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
3992#define EXTI_EMR1_EM22_Pos (22U)
3993#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
3994#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
3995#define EXTI_EMR1_EM23_Pos (23U)
3996#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
3997#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
3998#define EXTI_EMR1_EM24_Pos (24U)
3999#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
4000#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
4001#define EXTI_EMR1_EM25_Pos (25U)
4002#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
4003#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
4004#define EXTI_EMR1_EM26_Pos (26U)
4005#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
4006#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
4007#define EXTI_EMR1_EM27_Pos (27U)
4008#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
4009#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
4010#define EXTI_EMR1_EM28_Pos (28U)
4011#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
4012#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
4013#define EXTI_EMR1_EM29_Pos (29U)
4014#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
4015#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
4016#define EXTI_EMR1_EM30_Pos (30U)
4017#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
4018#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
4019#define EXTI_EMR1_EM31_Pos (31U)
4020#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
4021#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
4023/****************** Bit definition for EXTI_RTSR1 register ******************/
4024#define EXTI_RTSR1_RT0_Pos (0U)
4025#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)
4026#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk
4027#define EXTI_RTSR1_RT1_Pos (1U)
4028#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)
4029#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk
4030#define EXTI_RTSR1_RT2_Pos (2U)
4031#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)
4032#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk
4033#define EXTI_RTSR1_RT3_Pos (3U)
4034#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)
4035#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk
4036#define EXTI_RTSR1_RT4_Pos (4U)
4037#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)
4038#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk
4039#define EXTI_RTSR1_RT5_Pos (5U)
4040#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)
4041#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk
4042#define EXTI_RTSR1_RT6_Pos (6U)
4043#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)
4044#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk
4045#define EXTI_RTSR1_RT7_Pos (7U)
4046#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)
4047#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk
4048#define EXTI_RTSR1_RT8_Pos (8U)
4049#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)
4050#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk
4051#define EXTI_RTSR1_RT9_Pos (9U)
4052#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)
4053#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk
4054#define EXTI_RTSR1_RT10_Pos (10U)
4055#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)
4056#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk
4057#define EXTI_RTSR1_RT11_Pos (11U)
4058#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)
4059#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk
4060#define EXTI_RTSR1_RT12_Pos (12U)
4061#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)
4062#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk
4063#define EXTI_RTSR1_RT13_Pos (13U)
4064#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)
4065#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk
4066#define EXTI_RTSR1_RT14_Pos (14U)
4067#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)
4068#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk
4069#define EXTI_RTSR1_RT15_Pos (15U)
4070#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)
4071#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk
4072#define EXTI_RTSR1_RT16_Pos (16U)
4073#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos)
4074#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk
4075#define EXTI_RTSR1_RT17_Pos (17U)
4076#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos)
4077#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk
4078#define EXTI_RTSR1_RT19_Pos (19U)
4079#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos)
4080#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk
4081#define EXTI_RTSR1_RT20_Pos (20U)
4082#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos)
4083#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk
4084#define EXTI_RTSR1_RT21_Pos (21U)
4085#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos)
4086#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk
4087#define EXTI_RTSR1_RT22_Pos (22U)
4088#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos)
4089#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk
4090#define EXTI_RTSR1_RT29_Pos (29U)
4091#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos)
4092#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk
4093#define EXTI_RTSR1_RT30_Pos (30U)
4094#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos)
4095#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk
4096#define EXTI_RTSR1_RT31_Pos (31U)
4097#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos)
4098#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk
4100/****************** Bit definition for EXTI_FTSR1 register ******************/
4101#define EXTI_FTSR1_FT0_Pos (0U)
4102#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)
4103#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk
4104#define EXTI_FTSR1_FT1_Pos (1U)
4105#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)
4106#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk
4107#define EXTI_FTSR1_FT2_Pos (2U)
4108#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)
4109#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk
4110#define EXTI_FTSR1_FT3_Pos (3U)
4111#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)
4112#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk
4113#define EXTI_FTSR1_FT4_Pos (4U)
4114#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)
4115#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk
4116#define EXTI_FTSR1_FT5_Pos (5U)
4117#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)
4118#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk
4119#define EXTI_FTSR1_FT6_Pos (6U)
4120#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)
4121#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk
4122#define EXTI_FTSR1_FT7_Pos (7U)
4123#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)
4124#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk
4125#define EXTI_FTSR1_FT8_Pos (8U)
4126#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)
4127#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk
4128#define EXTI_FTSR1_FT9_Pos (9U)
4129#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)
4130#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk
4131#define EXTI_FTSR1_FT10_Pos (10U)
4132#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)
4133#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk
4134#define EXTI_FTSR1_FT11_Pos (11U)
4135#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)
4136#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk
4137#define EXTI_FTSR1_FT12_Pos (12U)
4138#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)
4139#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk
4140#define EXTI_FTSR1_FT13_Pos (13U)
4141#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)
4142#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk
4143#define EXTI_FTSR1_FT14_Pos (14U)
4144#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)
4145#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk
4146#define EXTI_FTSR1_FT15_Pos (15U)
4147#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)
4148#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk
4149#define EXTI_FTSR1_FT16_Pos (16U)
4150#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos)
4151#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk
4152#define EXTI_FTSR1_FT17_Pos (17U)
4153#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos)
4154#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk
4155#define EXTI_FTSR1_FT19_Pos (19U)
4156#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos)
4157#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk
4158#define EXTI_FTSR1_FT20_Pos (20U)
4159#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos)
4160#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk
4161#define EXTI_FTSR1_FT21_Pos (21U)
4162#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos)
4163#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk
4164#define EXTI_FTSR1_FT22_Pos (22U)
4165#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos)
4166#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk
4167#define EXTI_FTSR1_FT29_Pos (29U)
4168#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos)
4169#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk
4170#define EXTI_FTSR1_FT30_Pos (30U)
4171#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos)
4172#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk
4173#define EXTI_FTSR1_FT31_Pos (31U)
4174#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos)
4175#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk
4177/****************** Bit definition for EXTI_SWIER1 register *****************/
4178#define EXTI_SWIER1_SWI0_Pos (0U)
4179#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)
4180#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk
4181#define EXTI_SWIER1_SWI1_Pos (1U)
4182#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)
4183#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk
4184#define EXTI_SWIER1_SWI2_Pos (2U)
4185#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)
4186#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk
4187#define EXTI_SWIER1_SWI3_Pos (3U)
4188#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)
4189#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk
4190#define EXTI_SWIER1_SWI4_Pos (4U)
4191#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)
4192#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk
4193#define EXTI_SWIER1_SWI5_Pos (5U)
4194#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)
4195#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk
4196#define EXTI_SWIER1_SWI6_Pos (6U)
4197#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)
4198#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk
4199#define EXTI_SWIER1_SWI7_Pos (7U)
4200#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)
4201#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk
4202#define EXTI_SWIER1_SWI8_Pos (8U)
4203#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)
4204#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk
4205#define EXTI_SWIER1_SWI9_Pos (9U)
4206#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)
4207#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk
4208#define EXTI_SWIER1_SWI10_Pos (10U)
4209#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)
4210#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk
4211#define EXTI_SWIER1_SWI11_Pos (11U)
4212#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)
4213#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk
4214#define EXTI_SWIER1_SWI12_Pos (12U)
4215#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)
4216#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk
4217#define EXTI_SWIER1_SWI13_Pos (13U)
4218#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)
4219#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk
4220#define EXTI_SWIER1_SWI14_Pos (14U)
4221#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)
4222#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk
4223#define EXTI_SWIER1_SWI15_Pos (15U)
4224#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)
4225#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk
4226#define EXTI_SWIER1_SWI16_Pos (16U)
4227#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos)
4228#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk
4229#define EXTI_SWIER1_SWI17_Pos (17U)
4230#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos)
4231#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk
4232#define EXTI_SWIER1_SWI19_Pos (19U)
4233#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos)
4234#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk
4235#define EXTI_SWIER1_SWI20_Pos (20U)
4236#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos)
4237#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk
4238#define EXTI_SWIER1_SWI21_Pos (21U)
4239#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos)
4240#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk
4241#define EXTI_SWIER1_SWI22_Pos (22U)
4242#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos)
4243#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk
4244#define EXTI_SWIER1_SWI29_Pos (29U)
4245#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos)
4246#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk
4247#define EXTI_SWIER1_SWI30_Pos (30U)
4248#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos)
4249#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk
4250#define EXTI_SWIER1_SWI31_Pos (31U)
4251#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos)
4252#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk
4254/******************* Bit definition for EXTI_PR1 register *******************/
4255#define EXTI_PR1_PIF0_Pos (0U)
4256#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos)
4257#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk
4258#define EXTI_PR1_PIF1_Pos (1U)
4259#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos)
4260#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk
4261#define EXTI_PR1_PIF2_Pos (2U)
4262#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos)
4263#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk
4264#define EXTI_PR1_PIF3_Pos (3U)
4265#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos)
4266#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk
4267#define EXTI_PR1_PIF4_Pos (4U)
4268#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos)
4269#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk
4270#define EXTI_PR1_PIF5_Pos (5U)
4271#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos)
4272#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk
4273#define EXTI_PR1_PIF6_Pos (6U)
4274#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos)
4275#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk
4276#define EXTI_PR1_PIF7_Pos (7U)
4277#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos)
4278#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk
4279#define EXTI_PR1_PIF8_Pos (8U)
4280#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos)
4281#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk
4282#define EXTI_PR1_PIF9_Pos (9U)
4283#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos)
4284#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk
4285#define EXTI_PR1_PIF10_Pos (10U)
4286#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos)
4287#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk
4288#define EXTI_PR1_PIF11_Pos (11U)
4289#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos)
4290#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk
4291#define EXTI_PR1_PIF12_Pos (12U)
4292#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos)
4293#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk
4294#define EXTI_PR1_PIF13_Pos (13U)
4295#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos)
4296#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk
4297#define EXTI_PR1_PIF14_Pos (14U)
4298#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos)
4299#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk
4300#define EXTI_PR1_PIF15_Pos (15U)
4301#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos)
4302#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk
4303#define EXTI_PR1_PIF16_Pos (16U)
4304#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos)
4305#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk
4306#define EXTI_PR1_PIF17_Pos (17U)
4307#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos)
4308#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk
4309#define EXTI_PR1_PIF19_Pos (19U)
4310#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos)
4311#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk
4312#define EXTI_PR1_PIF20_Pos (20U)
4313#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos)
4314#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk
4315#define EXTI_PR1_PIF21_Pos (21U)
4316#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos)
4317#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk
4318#define EXTI_PR1_PIF22_Pos (22U)
4319#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos)
4320#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk
4321#define EXTI_PR1_PIF29_Pos (29U)
4322#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos)
4323#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk
4324#define EXTI_PR1_PIF30_Pos (30U)
4325#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos)
4326#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk
4327#define EXTI_PR1_PIF31_Pos (31U)
4328#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos)
4329#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk
4331/******************* Bit definition for EXTI_IMR2 register ******************/
4332#define EXTI_IMR2_IM32_Pos (0U)
4333#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
4334#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
4335#define EXTI_IMR2_IM33_Pos (1U)
4336#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
4337#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
4338#define EXTI_IMR2_IM34_Pos (2U)
4339#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
4340#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
4341#define EXTI_IMR2_IM35_Pos (3U)
4342#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
4343#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
4344#define EXTI_IMR2_IM36_Pos (4U)
4345#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
4346#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
4347#define EXTI_IMR2_IM37_Pos (5U)
4348#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
4349#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
4350#define EXTI_IMR2_IM38_Pos (6U)
4351#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
4352#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
4353#define EXTI_IMR2_IM39_Pos (7U)
4354#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
4355#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
4356#define EXTI_IMR2_IM40_Pos (8U)
4357#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)
4358#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk
4359#define EXTI_IMR2_IM41_Pos (9U)
4360#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)
4361#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk
4362#define EXTI_IMR2_IM42_Pos (10U)
4363#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos)
4364#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk
4365#define EXTI_IMR2_IM_Pos (0U)
4366#define EXTI_IMR2_IM_Msk (0x7FFUL << EXTI_IMR2_IM_Pos)
4367#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
4369/******************* Bit definition for EXTI_EMR2 register ******************/
4370#define EXTI_EMR2_EM32_Pos (0U)
4371#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
4372#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
4373#define EXTI_EMR2_EM33_Pos (1U)
4374#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
4375#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
4376#define EXTI_EMR2_EM34_Pos (2U)
4377#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
4378#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
4379#define EXTI_EMR2_EM35_Pos (3U)
4380#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
4381#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
4382#define EXTI_EMR2_EM36_Pos (4U)
4383#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
4384#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
4385#define EXTI_EMR2_EM37_Pos (5U)
4386#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
4387#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
4388#define EXTI_EMR2_EM38_Pos (6U)
4389#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
4390#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
4391#define EXTI_EMR2_EM39_Pos (7U)
4392#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
4393#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
4394#define EXTI_EMR2_EM40_Pos (8U)
4395#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)
4396#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk
4397#define EXTI_EMR2_EM41_Pos (9U)
4398#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)
4399#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk
4400#define EXTI_EMR2_EM42_Pos (10U)
4401#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos)
4402#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk
4403#define EXTI_EMR2_EM_Pos (0U)
4404#define EXTI_EMR2_EM_Msk (0x7FFUL << EXTI_EMR2_EM_Pos)
4405#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
4407/****************** Bit definition for EXTI_RTSR2 register ******************/
4408#define EXTI_RTSR2_RT32_Pos (0U)
4409#define EXTI_RTSR2_RT32_Msk (0x1UL << EXTI_RTSR2_RT32_Pos)
4410#define EXTI_RTSR2_RT32 EXTI_RTSR2_RT32_Msk
4411#define EXTI_RTSR2_RT33_Pos (1U)
4412#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos)
4413#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk
4414#define EXTI_RTSR2_RT38_Pos (6U)
4415#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos)
4416#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk
4417#define EXTI_RTSR2_RT39_Pos (7U)
4418#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos)
4419#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk
4420#define EXTI_RTSR2_RT40_Pos (8U)
4421#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos)
4422#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk
4423#define EXTI_RTSR2_RT41_Pos (9U)
4424#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos)
4425#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk
4427/****************** Bit definition for EXTI_FTSR2 register ******************/
4428#define EXTI_FTSR2_FT32_Pos (0U)
4429#define EXTI_FTSR2_FT32_Msk (0x1UL << EXTI_FTSR2_FT32_Pos)
4430#define EXTI_FTSR2_FT32 EXTI_FTSR2_FT32_Msk
4431#define EXTI_FTSR2_FT33_Pos (1U)
4432#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos)
4433#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk
4434#define EXTI_FTSR2_FT38_Pos (6U)
4435#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos)
4436#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk
4437#define EXTI_FTSR2_FT39_Pos (7U)
4438#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos)
4439#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk
4440#define EXTI_FTSR2_FT40_Pos (8U)
4441#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos)
4442#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk
4443#define EXTI_FTSR2_FT41_Pos (9U)
4444#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos)
4445#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk
4447/****************** Bit definition for EXTI_SWIER2 register *****************/
4448#define EXTI_SWIER2_SWI32_Pos (0U)
4449#define EXTI_SWIER2_SWI32_Msk (0x1UL << EXTI_SWIER2_SWI32_Pos)
4450#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWI32_Msk
4451#define EXTI_SWIER2_SWI33_Pos (1U)
4452#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos)
4453#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk
4454#define EXTI_SWIER2_SWI38_Pos (6U)
4455#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos)
4456#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk
4457#define EXTI_SWIER2_SWI39_Pos (7U)
4458#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos)
4459#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk
4460#define EXTI_SWIER2_SWI40_Pos (8U)
4461#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos)
4462#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk
4463#define EXTI_SWIER2_SWI41_Pos (9U)
4464#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos)
4465#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk
4467/******************* Bit definition for EXTI_PR2 register *******************/
4468#define EXTI_PR2_PIF32_Pos (0U)
4469#define EXTI_PR2_PIF32_Msk (0x1UL << EXTI_PR2_PIF32_Pos)
4470#define EXTI_PR2_PIF32 EXTI_PR2_PIF32_Msk
4471#define EXTI_PR2_PIF33_Pos (1U)
4472#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos)
4473#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk
4474#define EXTI_PR2_PIF38_Pos (6U)
4475#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos)
4476#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk
4477#define EXTI_PR2_PIF39_Pos (7U)
4478#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos)
4479#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk
4480#define EXTI_PR2_PIF40_Pos (8U)
4481#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos)
4482#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk
4483#define EXTI_PR2_PIF41_Pos (9U)
4484#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos)
4485#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk
4487/******************************************************************************/
4488/* */
4489/* Flexible Datarate Controller Area Network */
4490/* */
4491/******************************************************************************/
4493/***************** Bit definition for FDCAN_CREL register *******************/
4494#define FDCAN_CREL_DAY_Pos (0U)
4495#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)
4496#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk
4497#define FDCAN_CREL_MON_Pos (8U)
4498#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)
4499#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk
4500#define FDCAN_CREL_YEAR_Pos (16U)
4501#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)
4502#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk
4503#define FDCAN_CREL_SUBSTEP_Pos (20U)
4504#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)
4505#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk
4506#define FDCAN_CREL_STEP_Pos (24U)
4507#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)
4508#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk
4509#define FDCAN_CREL_REL_Pos (28U)
4510#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)
4511#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk
4513/***************** Bit definition for FDCAN_ENDN register *******************/
4514#define FDCAN_ENDN_ETV_Pos (0U)
4515#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)
4516#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk
4518/***************** Bit definition for FDCAN_DBTP register *******************/
4519#define FDCAN_DBTP_DSJW_Pos (0U)
4520#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)
4521#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk
4522#define FDCAN_DBTP_DTSEG2_Pos (4U)
4523#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)
4524#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk
4525#define FDCAN_DBTP_DTSEG1_Pos (8U)
4526#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)
4527#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk
4528#define FDCAN_DBTP_DBRP_Pos (16U)
4529#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)
4530#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk
4531#define FDCAN_DBTP_TDC_Pos (23U)
4532#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)
4533#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk
4535/***************** Bit definition for FDCAN_TEST register *******************/
4536#define FDCAN_TEST_LBCK_Pos (4U)
4537#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)
4538#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk
4539#define FDCAN_TEST_TX_Pos (5U)
4540#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)
4541#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk
4542#define FDCAN_TEST_RX_Pos (7U)
4543#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)
4544#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk
4546/***************** Bit definition for FDCAN_RWD register ********************/
4547#define FDCAN_RWD_WDC_Pos (0U)
4548#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)
4549#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk
4550#define FDCAN_RWD_WDV_Pos (8U)
4551#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)
4552#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk
4554/***************** Bit definition for FDCAN_CCCR register ********************/
4555#define FDCAN_CCCR_INIT_Pos (0U)
4556#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)
4557#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk
4558#define FDCAN_CCCR_CCE_Pos (1U)
4559#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)
4560#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk
4561#define FDCAN_CCCR_ASM_Pos (2U)
4562#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)
4563#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk
4564#define FDCAN_CCCR_CSA_Pos (3U)
4565#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)
4566#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk
4567#define FDCAN_CCCR_CSR_Pos (4U)
4568#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)
4569#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk
4570#define FDCAN_CCCR_MON_Pos (5U)
4571#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)
4572#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk
4573#define FDCAN_CCCR_DAR_Pos (6U)
4574#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)
4575#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk
4576#define FDCAN_CCCR_TEST_Pos (7U)
4577#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)
4578#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk
4579#define FDCAN_CCCR_FDOE_Pos (8U)
4580#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)
4581#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk
4582#define FDCAN_CCCR_BRSE_Pos (9U)
4583#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)
4584#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk
4585#define FDCAN_CCCR_PXHD_Pos (12U)
4586#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)
4587#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk
4588#define FDCAN_CCCR_EFBI_Pos (13U)
4589#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)
4590#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk
4591#define FDCAN_CCCR_TXP_Pos (14U)
4592#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)
4593#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk
4594#define FDCAN_CCCR_NISO_Pos (15U)
4595#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)
4596#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk
4598/***************** Bit definition for FDCAN_NBTP register ********************/
4599#define FDCAN_NBTP_NTSEG2_Pos (0U)
4600#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)
4601#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk
4602#define FDCAN_NBTP_NTSEG1_Pos (8U)
4603#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)
4604#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk
4605#define FDCAN_NBTP_NBRP_Pos (16U)
4606#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)
4607#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk
4608#define FDCAN_NBTP_NSJW_Pos (25U)
4609#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)
4610#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk
4612/***************** Bit definition for FDCAN_TSCC register ********************/
4613#define FDCAN_TSCC_TSS_Pos (0U)
4614#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)
4615#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk
4616#define FDCAN_TSCC_TCP_Pos (16U)
4617#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)
4618#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk
4620/***************** Bit definition for FDCAN_TSCV register ********************/
4621#define FDCAN_TSCV_TSC_Pos (0U)
4622#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)
4623#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk
4625/***************** Bit definition for FDCAN_TOCC register ********************/
4626#define FDCAN_TOCC_ETOC_Pos (0U)
4627#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)
4628#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk
4629#define FDCAN_TOCC_TOS_Pos (1U)
4630#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)
4631#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk
4632#define FDCAN_TOCC_TOP_Pos (16U)
4633#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)
4634#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk
4636/***************** Bit definition for FDCAN_TOCV register ********************/
4637#define FDCAN_TOCV_TOC_Pos (0U)
4638#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)
4639#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk
4641/***************** Bit definition for FDCAN_ECR register *********************/
4642#define FDCAN_ECR_TEC_Pos (0U)
4643#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)
4644#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk
4645#define FDCAN_ECR_REC_Pos (8U)
4646#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)
4647#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk
4648#define FDCAN_ECR_RP_Pos (15U)
4649#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)
4650#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk
4651#define FDCAN_ECR_CEL_Pos (16U)
4652#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)
4653#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk
4655/***************** Bit definition for FDCAN_PSR register *********************/
4656#define FDCAN_PSR_LEC_Pos (0U)
4657#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)
4658#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk
4659#define FDCAN_PSR_ACT_Pos (3U)
4660#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)
4661#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk
4662#define FDCAN_PSR_EP_Pos (5U)
4663#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)
4664#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk
4665#define FDCAN_PSR_EW_Pos (6U)
4666#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)
4667#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk
4668#define FDCAN_PSR_BO_Pos (7U)
4669#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)
4670#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk
4671#define FDCAN_PSR_DLEC_Pos (8U)
4672#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)
4673#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk
4674#define FDCAN_PSR_RESI_Pos (11U)
4675#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)
4676#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk
4677#define FDCAN_PSR_RBRS_Pos (12U)
4678#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)
4679#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk
4680#define FDCAN_PSR_REDL_Pos (13U)
4681#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)
4682#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk
4683#define FDCAN_PSR_PXE_Pos (14U)
4684#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)
4685#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk
4686#define FDCAN_PSR_TDCV_Pos (16U)
4687#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)
4688#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk
4690/***************** Bit definition for FDCAN_TDCR register ********************/
4691#define FDCAN_TDCR_TDCF_Pos (0U)
4692#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)
4693#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk
4694#define FDCAN_TDCR_TDCO_Pos (8U)
4695#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)
4696#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk
4698/***************** Bit definition for FDCAN_IR register **********************/
4699#define FDCAN_IR_RF0N_Pos (0U)
4700#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)
4701#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk
4702#define FDCAN_IR_RF0F_Pos (1U)
4703#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)
4704#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk
4705#define FDCAN_IR_RF0L_Pos (2U)
4706#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)
4707#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk
4708#define FDCAN_IR_RF1N_Pos (3U)
4709#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)
4710#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk
4711#define FDCAN_IR_RF1F_Pos (4U)
4712#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)
4713#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk
4714#define FDCAN_IR_RF1L_Pos (5U)
4715#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)
4716#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk
4717#define FDCAN_IR_HPM_Pos (6U)
4718#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)
4719#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk
4720#define FDCAN_IR_TC_Pos (7U)
4721#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)
4722#define FDCAN_IR_TC FDCAN_IR_TC_Msk
4723#define FDCAN_IR_TCF_Pos (8U)
4724#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)
4725#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk
4726#define FDCAN_IR_TFE_Pos (9U)
4727#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)
4728#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk
4729#define FDCAN_IR_TEFN_Pos (10U)
4730#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)
4731#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk
4732#define FDCAN_IR_TEFF_Pos (11U)
4733#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)
4734#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk
4735#define FDCAN_IR_TEFL_Pos (12U)
4736#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)
4737#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk
4738#define FDCAN_IR_TSW_Pos (13U)
4739#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)
4740#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk
4741#define FDCAN_IR_MRAF_Pos (14U)
4742#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)
4743#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk
4744#define FDCAN_IR_TOO_Pos (15U)
4745#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)
4746#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk
4747#define FDCAN_IR_ELO_Pos (16U)
4748#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)
4749#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk
4750#define FDCAN_IR_EP_Pos (17U)
4751#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)
4752#define FDCAN_IR_EP FDCAN_IR_EP_Msk
4753#define FDCAN_IR_EW_Pos (18U)
4754#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)
4755#define FDCAN_IR_EW FDCAN_IR_EW_Msk
4756#define FDCAN_IR_BO_Pos (19U)
4757#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)
4758#define FDCAN_IR_BO FDCAN_IR_BO_Msk
4759#define FDCAN_IR_WDI_Pos (20U)
4760#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)
4761#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk
4762#define FDCAN_IR_PEA_Pos (21U)
4763#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)
4764#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk
4765#define FDCAN_IR_PED_Pos (22U)
4766#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)
4767#define FDCAN_IR_PED FDCAN_IR_PED_Msk
4768#define FDCAN_IR_ARA_Pos (23U)
4769#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)
4770#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk
4772/***************** Bit definition for FDCAN_IE register **********************/
4773#define FDCAN_IE_RF0NE_Pos (0U)
4774#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)
4775#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk
4776#define FDCAN_IE_RF0FE_Pos (1U)
4777#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)
4778#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk
4779#define FDCAN_IE_RF0LE_Pos (2U)
4780#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)
4781#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk
4782#define FDCAN_IE_RF1NE_Pos (3U)
4783#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)
4784#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk
4785#define FDCAN_IE_RF1FE_Pos (4U)
4786#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)
4787#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk
4788#define FDCAN_IE_RF1LE_Pos (5U)
4789#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)
4790#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk
4791#define FDCAN_IE_HPME_Pos (6U)
4792#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)
4793#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk
4794#define FDCAN_IE_TCE_Pos (7U)
4795#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)
4796#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk
4797#define FDCAN_IE_TCFE_Pos (8U)
4798#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)
4799#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk
4800#define FDCAN_IE_TFEE_Pos (9U)
4801#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)
4802#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk
4803#define FDCAN_IE_TEFNE_Pos (10U)
4804#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)
4805#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk
4806#define FDCAN_IE_TEFFE_Pos (11U)
4807#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)
4808#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk
4809#define FDCAN_IE_TEFLE_Pos (12U)
4810#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)
4811#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk
4812#define FDCAN_IE_TSWE_Pos (13U)
4813#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)
4814#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk
4815#define FDCAN_IE_MRAFE_Pos (14U)
4816#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)
4817#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk
4818#define FDCAN_IE_TOOE_Pos (15U)
4819#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)
4820#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk
4821#define FDCAN_IE_ELOE_Pos (16U)
4822#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)
4823#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk
4824#define FDCAN_IE_EPE_Pos (17U)
4825#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)
4826#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk
4827#define FDCAN_IE_EWE_Pos (18U)
4828#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)
4829#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk
4830#define FDCAN_IE_BOE_Pos (19U)
4831#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)
4832#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk
4833#define FDCAN_IE_WDIE_Pos (20U)
4834#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)
4835#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk
4836#define FDCAN_IE_PEAE_Pos (21U)
4837#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)
4838#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk
4839#define FDCAN_IE_PEDE_Pos (22U)
4840#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)
4841#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk
4842#define FDCAN_IE_ARAE_Pos (23U)
4843#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)
4844#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk
4846/***************** Bit definition for FDCAN_ILS register **********************/
4847#define FDCAN_ILS_RXFIFO0_Pos (0U)
4848#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos)
4849#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk
4852#define FDCAN_ILS_RXFIFO1_Pos (1U)
4853#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos)
4854#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk
4857#define FDCAN_ILS_SMSG_Pos (2U)
4858#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos)
4859#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk
4862#define FDCAN_ILS_TFERR_Pos (3U)
4863#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos)
4864#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk
4868#define FDCAN_ILS_MISC_Pos (4U)
4869#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos)
4870#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk
4873#define FDCAN_ILS_BERR_Pos (5U)
4874#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos)
4875#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk
4877#define FDCAN_ILS_PERR_Pos (6U)
4878#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos)
4879#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk
4886/***************** Bit definition for FDCAN_ILE register **********************/
4887#define FDCAN_ILE_EINT0_Pos (0U)
4888#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)
4889#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk
4890#define FDCAN_ILE_EINT1_Pos (1U)
4891#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)
4892#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk
4894/***************** Bit definition for FDCAN_RXGFC register ********************/
4895#define FDCAN_RXGFC_RRFE_Pos (0U)
4896#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos)
4897#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk
4898#define FDCAN_RXGFC_RRFS_Pos (1U)
4899#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos)
4900#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk
4901#define FDCAN_RXGFC_ANFE_Pos (2U)
4902#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos)
4903#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk
4904#define FDCAN_RXGFC_ANFS_Pos (4U)
4905#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos)
4906#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk
4907#define FDCAN_RXGFC_F1OM_Pos (8U)
4908#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos)
4909#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk
4910#define FDCAN_RXGFC_F0OM_Pos (9U)
4911#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos)
4912#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk
4913#define FDCAN_RXGFC_LSS_Pos (16U)
4914#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos)
4915#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk
4916#define FDCAN_RXGFC_LSE_Pos (24U)
4917#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos)
4918#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk
4920/***************** Bit definition for FDCAN_XIDAM register ********************/
4921#define FDCAN_XIDAM_EIDM_Pos (0U)
4922#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)
4923#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk
4925/***************** Bit definition for FDCAN_HPMS register *********************/
4926#define FDCAN_HPMS_BIDX_Pos (0U)
4927#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos)
4928#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk
4929#define FDCAN_HPMS_MSI_Pos (6U)
4930#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)
4931#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk
4932#define FDCAN_HPMS_FIDX_Pos (8U)
4933#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos)
4934#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk
4935#define FDCAN_HPMS_FLST_Pos (15U)
4936#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)
4937#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk
4939/***************** Bit definition for FDCAN_RXF0S register ********************/
4940#define FDCAN_RXF0S_F0FL_Pos (0U)
4941#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos)
4942#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk
4943#define FDCAN_RXF0S_F0GI_Pos (8U)
4944#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos)
4945#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk
4946#define FDCAN_RXF0S_F0PI_Pos (16U)
4947#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos)
4948#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk
4949#define FDCAN_RXF0S_F0F_Pos (24U)
4950#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)
4951#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk
4952#define FDCAN_RXF0S_RF0L_Pos (25U)
4953#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)
4954#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk
4956/***************** Bit definition for FDCAN_RXF0A register ********************/
4957#define FDCAN_RXF0A_F0AI_Pos (0U)
4958#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos)
4959#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk
4961/***************** Bit definition for FDCAN_RXF1S register ********************/
4962#define FDCAN_RXF1S_F1FL_Pos (0U)
4963#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos)
4964#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk
4965#define FDCAN_RXF1S_F1GI_Pos (8U)
4966#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos)
4967#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk
4968#define FDCAN_RXF1S_F1PI_Pos (16U)
4969#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos)
4970#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk
4971#define FDCAN_RXF1S_F1F_Pos (24U)
4972#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)
4973#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk
4974#define FDCAN_RXF1S_RF1L_Pos (25U)
4975#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)
4976#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk
4978/***************** Bit definition for FDCAN_RXF1A register ********************/
4979#define FDCAN_RXF1A_F1AI_Pos (0U)
4980#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos)
4981#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk
4983/***************** Bit definition for FDCAN_TXBC register *********************/
4984#define FDCAN_TXBC_TFQM_Pos (24U)
4985#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)
4986#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk
4988/***************** Bit definition for FDCAN_TXFQS register *********************/
4989#define FDCAN_TXFQS_TFFL_Pos (0U)
4990#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos)
4991#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk
4992#define FDCAN_TXFQS_TFGI_Pos (8U)
4993#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos)
4994#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk
4995#define FDCAN_TXFQS_TFQPI_Pos (16U)
4996#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos)
4997#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk
4998#define FDCAN_TXFQS_TFQF_Pos (21U)
4999#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)
5000#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk
5002/***************** Bit definition for FDCAN_TXBRP register *********************/
5003#define FDCAN_TXBRP_TRP_Pos (0U)
5004#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos)
5005#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk
5007/***************** Bit definition for FDCAN_TXBAR register *********************/
5008#define FDCAN_TXBAR_AR_Pos (0U)
5009#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos)
5010#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk
5012/***************** Bit definition for FDCAN_TXBCR register *********************/
5013#define FDCAN_TXBCR_CR_Pos (0U)
5014#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos)
5015#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk
5017/***************** Bit definition for FDCAN_TXBTO register *********************/
5018#define FDCAN_TXBTO_TO_Pos (0U)
5019#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos)
5020#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk
5022/***************** Bit definition for FDCAN_TXBCF register *********************/
5023#define FDCAN_TXBCF_CF_Pos (0U)
5024#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos)
5025#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk
5027/***************** Bit definition for FDCAN_TXBTIE register ********************/
5028#define FDCAN_TXBTIE_TIE_Pos (0U)
5029#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos)
5030#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk
5032/***************** Bit definition for FDCAN_ TXBCIE register *******************/
5033#define FDCAN_TXBCIE_CFIE_Pos (0U)
5034#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos)
5035#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk
5037/***************** Bit definition for FDCAN_TXEFS register *********************/
5038#define FDCAN_TXEFS_EFFL_Pos (0U)
5039#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos)
5040#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk
5041#define FDCAN_TXEFS_EFGI_Pos (8U)
5042#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos)
5043#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk
5044#define FDCAN_TXEFS_EFPI_Pos (16U)
5045#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos)
5046#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk
5047#define FDCAN_TXEFS_EFF_Pos (24U)
5048#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)
5049#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk
5050#define FDCAN_TXEFS_TEFL_Pos (25U)
5051#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)
5052#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk
5054/***************** Bit definition for FDCAN_TXEFA register *********************/
5055#define FDCAN_TXEFA_EFAI_Pos (0U)
5056#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos)
5057#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk
5061/***************** Bit definition for FDCAN_CKDIV register *********************/
5062#define FDCAN_CKDIV_PDIV_Pos (0U)
5063#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos)
5064#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk
5066/******************************************************************************/
5067/* */
5068/* FLASH */
5069/* */
5070/******************************************************************************/
5071/******************* Bits definition for FLASH_ACR register *****************/
5072#define FLASH_ACR_LATENCY_Pos (0U)
5073#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
5074#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
5075#define FLASH_ACR_LATENCY_0WS (0x00000000U)
5076#define FLASH_ACR_LATENCY_1WS (0x00000001U)
5077#define FLASH_ACR_LATENCY_2WS (0x00000002U)
5078#define FLASH_ACR_LATENCY_3WS (0x00000003U)
5079#define FLASH_ACR_LATENCY_4WS (0x00000004U)
5080#define FLASH_ACR_LATENCY_5WS (0x00000005U)
5081#define FLASH_ACR_LATENCY_6WS (0x00000006U)
5082#define FLASH_ACR_LATENCY_7WS (0x00000007U)
5083#define FLASH_ACR_LATENCY_8WS (0x00000008U)
5084#define FLASH_ACR_LATENCY_9WS (0x00000009U)
5085#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
5086#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
5087#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
5088#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
5089#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
5090#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
5091#define FLASH_ACR_PRFTEN_Pos (8U)
5092#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
5093#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
5094#define FLASH_ACR_ICEN_Pos (9U)
5095#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
5096#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
5097#define FLASH_ACR_DCEN_Pos (10U)
5098#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
5099#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
5100#define FLASH_ACR_ICRST_Pos (11U)
5101#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
5102#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
5103#define FLASH_ACR_DCRST_Pos (12U)
5104#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
5105#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
5106#define FLASH_ACR_RUN_PD_Pos (13U)
5107#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)
5108#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk
5109#define FLASH_ACR_SLEEP_PD_Pos (14U)
5110#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)
5111#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk
5112#define FLASH_ACR_DBG_SWEN_Pos (18U)
5113#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos)
5114#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk
5116/******************* Bits definition for FLASH_SR register ******************/
5117#define FLASH_SR_EOP_Pos (0U)
5118#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
5119#define FLASH_SR_EOP FLASH_SR_EOP_Msk
5120#define FLASH_SR_OPERR_Pos (1U)
5121#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
5122#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
5123#define FLASH_SR_PROGERR_Pos (3U)
5124#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)
5125#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
5126#define FLASH_SR_WRPERR_Pos (4U)
5127#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
5128#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
5129#define FLASH_SR_PGAERR_Pos (5U)
5130#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
5131#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
5132#define FLASH_SR_SIZERR_Pos (6U)
5133#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)
5134#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
5135#define FLASH_SR_PGSERR_Pos (7U)
5136#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
5137#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
5138#define FLASH_SR_MISERR_Pos (8U)
5139#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)
5140#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
5141#define FLASH_SR_FASTERR_Pos (9U)
5142#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)
5143#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
5144#define FLASH_SR_RDERR_Pos (14U)
5145#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
5146#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
5147#define FLASH_SR_OPTVERR_Pos (15U)
5148#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)
5149#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
5150#define FLASH_SR_BSY_Pos (16U)
5151#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
5152#define FLASH_SR_BSY FLASH_SR_BSY_Msk
5153
5154/******************* Bits definition for FLASH_CR register ******************/
5155#define FLASH_CR_PG_Pos (0U)
5156#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
5157#define FLASH_CR_PG FLASH_CR_PG_Msk
5158#define FLASH_CR_PER_Pos (1U)
5159#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
5160#define FLASH_CR_PER FLASH_CR_PER_Msk
5161#define FLASH_CR_MER1_Pos (2U)
5162#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)
5163#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
5164#define FLASH_CR_PNB_Pos (3U)
5165#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos)
5166#define FLASH_CR_PNB FLASH_CR_PNB_Msk
5167#define FLASH_CR_BKER_Pos (11U)
5168#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos)
5169#define FLASH_CR_BKER FLASH_CR_BKER_Msk
5170#define FLASH_CR_MER2_Pos (15U)
5171#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
5172#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
5173#define FLASH_CR_STRT_Pos (16U)
5174#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
5175#define FLASH_CR_STRT FLASH_CR_STRT_Msk
5176#define FLASH_CR_OPTSTRT_Pos (17U)
5177#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)
5178#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
5179#define FLASH_CR_FSTPG_Pos (18U)
5180#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)
5181#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
5182#define FLASH_CR_EOPIE_Pos (24U)
5183#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
5184#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
5185#define FLASH_CR_ERRIE_Pos (25U)
5186#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
5187#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
5188#define FLASH_CR_RDERRIE_Pos (26U)
5189#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)
5190#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
5191#define FLASH_CR_OBL_LAUNCH_Pos (27U)
5192#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)
5193#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
5194#define FLASH_CR_SEC_PROT1_Pos (28U)
5195#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos)
5196#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
5197#define FLASH_CR_SEC_PROT2_Pos (29U)
5198#define FLASH_CR_SEC_PROT2_Msk (0x1UL << FLASH_CR_SEC_PROT2_Pos)
5199#define FLASH_CR_SEC_PROT2 FLASH_CR_SEC_PROT2_Msk
5200#define FLASH_CR_OPTLOCK_Pos (30U)
5201#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)
5202#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
5203#define FLASH_CR_LOCK_Pos (31U)
5204#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
5205#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
5206
5207/******************* Bits definition for FLASH_ECCR register ***************/
5208#define FLASH_ECCR_ADDR_ECC_Pos (0U)
5209#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)
5210#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
5211#define FLASH_ECCR_BK_ECC_Pos (21U)
5212#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos)
5213#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
5214#define FLASH_ECCR_SYSF_ECC_Pos (22U)
5215#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)
5216#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
5217#define FLASH_ECCR_ECCIE_Pos (24U)
5218#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos)
5219#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
5220#define FLASH_ECCR_ECCC2_Pos (28U)
5221#define FLASH_ECCR_ECCC2_Msk (0x1UL << FLASH_ECCR_ECCC2_Pos)
5222#define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
5223#define FLASH_ECCR_ECCD2_Pos (29U)
5224#define FLASH_ECCR_ECCD2_Msk (0x1UL << FLASH_ECCR_ECCD2_Pos)
5225#define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
5226#define FLASH_ECCR_ECCC_Pos (30U)
5227#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)
5228#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
5229#define FLASH_ECCR_ECCD_Pos (31U)
5230#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)
5231#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
5232
5233/******************* Bits definition for FLASH_OPTR register ***************/
5234#define FLASH_OPTR_RDP_Pos (0U)
5235#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)
5236#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
5237#define FLASH_OPTR_BOR_LEV_Pos (8U)
5238#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos)
5239#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
5240#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos)
5241#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos)
5242#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos)
5243#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos)
5244#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos)
5245#define FLASH_OPTR_nRST_STOP_Pos (12U)
5246#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)
5247#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
5248#define FLASH_OPTR_nRST_STDBY_Pos (13U)
5249#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)
5250#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
5251#define FLASH_OPTR_nRST_SHDW_Pos (14U)
5252#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)
5253#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
5254#define FLASH_OPTR_IWDG_SW_Pos (16U)
5255#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)
5256#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
5257#define FLASH_OPTR_IWDG_STOP_Pos (17U)
5258#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)
5259#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
5260#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
5261#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)
5262#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
5263#define FLASH_OPTR_WWDG_SW_Pos (19U)
5264#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)
5265#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
5266#define FLASH_OPTR_BFB2_Pos (20U)
5267#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos)
5268#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
5269#define FLASH_OPTR_DBANK_Pos (22U)
5270#define FLASH_OPTR_DBANK_Msk (0x1UL << FLASH_OPTR_DBANK_Pos)
5271#define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
5272#define FLASH_OPTR_nBOOT1_Pos (23U)
5273#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)
5274#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
5275#define FLASH_OPTR_SRAM_PE_Pos (24U)
5276#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos)
5277#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
5278#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
5279#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)
5280#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
5281#define FLASH_OPTR_nSWBOOT0_Pos (26U)
5282#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)
5283#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
5284#define FLASH_OPTR_nBOOT0_Pos (27U)
5285#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos)
5286#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
5287#define FLASH_OPTR_NRST_MODE_Pos (28U)
5288#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos)
5289#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
5290#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos)
5291#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos)
5292#define FLASH_OPTR_IRHEN_Pos (30U)
5293#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos)
5294#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
5295
5296/****************** Bits definition for FLASH_PCROP1SR register **********/
5297#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
5298#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)
5299#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
5300
5301/****************** Bits definition for FLASH_PCROP1ER register ***********/
5302#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
5303#define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)
5304#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
5305#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
5306#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)
5307#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
5308
5309/****************** Bits definition for FLASH_WRP1AR register ***************/
5310#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
5311#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)
5312#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
5313#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
5314#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)
5315#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
5316
5317/****************** Bits definition for FLASH_WRPB1R register ***************/
5318#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
5319#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)
5320#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
5321#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
5322#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)
5323#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
5324
5325/****************** Bits definition for FLASH_PCROP2SR register **********/
5326#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
5327#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)
5328#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
5329
5330/****************** Bits definition for FLASH_PCROP2ER register ***********/
5331#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
5332#define FLASH_PCROP2ER_PCROP2_END_Msk (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)
5333#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
5334
5335/****************** Bits definition for FLASH_WRP2AR register ***************/
5336#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
5337#define FLASH_WRP2AR_WRP2A_STRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)
5338#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
5339#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
5340#define FLASH_WRP2AR_WRP2A_END_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)
5341#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
5342
5343/****************** Bits definition for FLASH_WRP2BR register ***************/
5344#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
5345#define FLASH_WRP2BR_WRP2B_STRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)
5346#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
5347#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
5348#define FLASH_WRP2BR_WRP2B_END_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)
5349#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
5350
5351/****************** Bits definition for FLASH_SEC1R register **************/
5352#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
5353#define FLASH_SEC1R_SEC_SIZE1_Msk (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)
5354#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
5355#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
5356#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)
5357#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
5358
5359/****************** Bits definition for FLASH_SEC2R register **************/
5360#define FLASH_SEC2R_SEC_SIZE2_Pos (0U)
5361#define FLASH_SEC2R_SEC_SIZE2_Msk (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)
5362#define FLASH_SEC2R_SEC_SIZE2 FLASH_SEC2R_SEC_SIZE2_Msk
5363
5364/******************************************************************************/
5365/* */
5366/* Filter Mathematical ACcelerator unit (FMAC) */
5367/* */
5368/******************************************************************************/
5369/***************** Bit definition for FMAC_X1BUFCFG register ****************/
5370#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
5371#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)
5372#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk
5373#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
5374#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)
5375#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk
5376#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
5377#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos)
5378#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk
5379/***************** Bit definition for FMAC_X2BUFCFG register ****************/
5380#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
5381#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)
5382#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk
5383#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
5384#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)
5385#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk
5386/***************** Bit definition for FMAC_YBUFCFG register *****************/
5387#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
5388#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)
5389#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk
5390#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
5391#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)
5392#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk
5393#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
5394#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos)
5395#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk
5396/****************** Bit definition for FMAC_PARAM register ******************/
5397#define FMAC_PARAM_P_Pos (0U)
5398#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos)
5399#define FMAC_PARAM_P FMAC_PARAM_P_Msk
5400#define FMAC_PARAM_Q_Pos (8U)
5401#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos)
5402#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk
5403#define FMAC_PARAM_R_Pos (16U)
5404#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos)
5405#define FMAC_PARAM_R FMAC_PARAM_R_Msk
5406#define FMAC_PARAM_FUNC_Pos (24U)
5407#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos)
5408#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk
5409#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos)
5410#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos)
5411#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos)
5412#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos)
5413#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos)
5414#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos)
5415#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos)
5416#define FMAC_PARAM_START_Pos (31U)
5417#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos)
5418#define FMAC_PARAM_START FMAC_PARAM_START_Msk
5419/******************** Bit definition for FMAC_CR register *******************/
5420#define FMAC_CR_RIEN_Pos (0U)
5421#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos)
5422#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk
5423#define FMAC_CR_WIEN_Pos (1U)
5424#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos)
5425#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk
5426#define FMAC_CR_OVFLIEN_Pos (2U)
5427#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos)
5428#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk
5429#define FMAC_CR_UNFLIEN_Pos (3U)
5430#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos)
5431#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk
5432#define FMAC_CR_SATIEN_Pos (4U)
5433#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos)
5434#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk
5435#define FMAC_CR_DMAREN_Pos (8U)
5436#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos)
5437#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk
5438#define FMAC_CR_DMAWEN_Pos (9U)
5439#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos)
5440#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk
5441#define FMAC_CR_CLIPEN_Pos (15U)
5442#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos)
5443#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk
5444#define FMAC_CR_RESET_Pos (16U)
5445#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos)
5446#define FMAC_CR_RESET FMAC_CR_RESET_Msk
5447/******************* Bit definition for FMAC_SR register ********************/
5448#define FMAC_SR_YEMPTY_Pos (0U)
5449#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos)
5450#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk
5451#define FMAC_SR_X1FULL_Pos (1U)
5452#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos)
5453#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk
5454#define FMAC_SR_OVFL_Pos (8U)
5455#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos)
5456#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk
5457#define FMAC_SR_UNFL_Pos (9U)
5458#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos)
5459#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk
5460#define FMAC_SR_SAT_Pos (10U)
5461#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos)
5462#define FMAC_SR_SAT FMAC_SR_SAT_Msk
5463/****************** Bit definition for FMAC_WDATA register ******************/
5464#define FMAC_WDATA_WDATA_Pos (0U)
5465#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos)
5466#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk
5467/****************** Bit definition for FMACX_RDATA register *****************/
5468#define FMAC_RDATA_RDATA_Pos (0U)
5469#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos)
5470#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk
5472/******************************************************************************/
5473/* */
5474/* Flexible Memory Controller */
5475/* */
5476/******************************************************************************/
5477/****************** Bit definition for FMC_BCR1 register *******************/
5478#define FMC_BCR1_CCLKEN_Pos (20U)
5479#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
5480#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
5481#define FMC_BCR1_WFDIS_Pos (21U)
5482#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
5483#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
5485/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
5486#define FMC_BCRx_MBKEN_Pos (0U)
5487#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
5488#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
5489#define FMC_BCRx_MUXEN_Pos (1U)
5490#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
5491#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
5493#define FMC_BCRx_MTYP_Pos (2U)
5494#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
5495#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
5496#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
5497#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
5499#define FMC_BCRx_MWID_Pos (4U)
5500#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
5501#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
5502#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
5503#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
5505#define FMC_BCRx_FACCEN_Pos (6U)
5506#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
5507#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
5508#define FMC_BCRx_BURSTEN_Pos (8U)
5509#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
5510#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
5511#define FMC_BCRx_WAITPOL_Pos (9U)
5512#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
5513#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
5514#define FMC_BCRx_WAITCFG_Pos (11U)
5515#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
5516#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
5517#define FMC_BCRx_WREN_Pos (12U)
5518#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
5519#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
5520#define FMC_BCRx_WAITEN_Pos (13U)
5521#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
5522#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
5523#define FMC_BCRx_EXTMOD_Pos (14U)
5524#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
5525#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
5526#define FMC_BCRx_ASYNCWAIT_Pos (15U)
5527#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
5528#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
5530#define FMC_BCRx_CPSIZE_Pos (16U)
5531#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
5532#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
5533#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
5534#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
5535#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
5537#define FMC_BCRx_CBURSTRW_Pos (19U)
5538#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
5539#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
5541#define FMC_BCRx_NBLSET_Pos (22U)
5542#define FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos)
5543#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk
5544#define FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos)
5545#define FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos)
5547/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
5548#define FMC_BTRx_ADDSET_Pos (0U)
5549#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
5550#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
5551#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
5552#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
5553#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
5554#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
5556#define FMC_BTRx_ADDHLD_Pos (4U)
5557#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
5558#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
5559#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
5560#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
5561#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
5562#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
5564#define FMC_BTRx_DATAST_Pos (8U)
5565#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
5566#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
5567#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
5568#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
5569#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
5570#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
5571#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
5572#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
5573#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
5574#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
5576#define FMC_BTRx_BUSTURN_Pos (16U)
5577#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
5578#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
5579#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
5580#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
5581#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
5582#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
5584#define FMC_BTRx_CLKDIV_Pos (20U)
5585#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
5586#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
5587#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
5588#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
5589#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
5590#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
5592#define FMC_BTRx_DATLAT_Pos (24U)
5593#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
5594#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
5595#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
5596#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
5597#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
5598#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
5600#define FMC_BTRx_ACCMOD_Pos (28U)
5601#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
5602#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
5603#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
5604#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
5606#define FMC_BTRx_DATAHLD_Pos (30U)
5607#define FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos)
5608#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk
5609#define FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos)
5610#define FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos)
5612/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
5613#define FMC_BWTRx_ADDSET_Pos (0U)
5614#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
5615#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
5616#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
5617#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
5618#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
5619#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
5621#define FMC_BWTRx_ADDHLD_Pos (4U)
5622#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
5623#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
5624#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
5625#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
5626#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
5627#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
5629#define FMC_BWTRx_DATAST_Pos (8U)
5630#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
5631#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
5632#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
5633#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
5634#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
5635#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
5636#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
5637#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
5638#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
5639#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
5641#define FMC_BWTRx_BUSTURN_Pos (16U)
5642#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
5643#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
5644#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
5645#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
5646#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
5647#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
5649#define FMC_BWTRx_ACCMOD_Pos (28U)
5650#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
5651#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
5652#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
5653#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
5655#define FMC_BWTRx_DATAHLD_Pos (30U)
5656#define FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos)
5657#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk
5658#define FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos)
5659#define FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos)
5661/****************** Bit definition for FMC_PCSCNTR register ******************/
5662#define FMC_PCSCNTR_CSCOUNT_Pos (0U)
5663#define FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos)
5664#define FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk
5666#define FMC_PCSCNTR_CNTB1EN_Pos (16U)
5667#define FMC_PCSCNTR_CNTB1EN_Msk (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos)
5668#define FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk
5670#define FMC_PCSCNTR_CNTB2EN_Pos (17U)
5671#define FMC_PCSCNTR_CNTB2EN_Msk (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos)
5672#define FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk
5674#define FMC_PCSCNTR_CNTB3EN_Pos (18U)
5675#define FMC_PCSCNTR_CNTB3EN_Msk (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos)
5676#define FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk
5678#define FMC_PCSCNTR_CNTB4EN_Pos (19U)
5679#define FMC_PCSCNTR_CNTB4EN_Msk (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos)
5680#define FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk
5682/****************** Bit definition for FMC_PCR register ********************/
5683#define FMC_PCR_PWAITEN_Pos (1U)
5684#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
5685#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
5686#define FMC_PCR_PBKEN_Pos (2U)
5687#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
5688#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
5689#define FMC_PCR_PTYP_Pos (3U)
5690#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
5691#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
5693#define FMC_PCR_PWID_Pos (4U)
5694#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
5695#define FMC_PCR_PWID FMC_PCR_PWID_Msk
5696#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
5697#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
5699#define FMC_PCR_ECCEN_Pos (6U)
5700#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
5701#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
5703#define FMC_PCR_TCLR_Pos (9U)
5704#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
5705#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
5706#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
5707#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
5708#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
5709#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
5711#define FMC_PCR_TAR_Pos (13U)
5712#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
5713#define FMC_PCR_TAR FMC_PCR_TAR_Msk
5714#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
5715#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
5716#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
5717#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
5719#define FMC_PCR_ECCPS_Pos (17U)
5720#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
5721#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
5722#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
5723#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
5724#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
5726/******************* Bit definition for FMC_SR register ********************/
5727#define FMC_SR_IRS_Pos (0U)
5728#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
5729#define FMC_SR_IRS FMC_SR_IRS_Msk
5730#define FMC_SR_ILS_Pos (1U)
5731#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
5732#define FMC_SR_ILS FMC_SR_ILS_Msk
5733#define FMC_SR_IFS_Pos (2U)
5734#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
5735#define FMC_SR_IFS FMC_SR_IFS_Msk
5736#define FMC_SR_IREN_Pos (3U)
5737#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
5738#define FMC_SR_IREN FMC_SR_IREN_Msk
5739#define FMC_SR_ILEN_Pos (4U)
5740#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
5741#define FMC_SR_ILEN FMC_SR_ILEN_Msk
5742#define FMC_SR_IFEN_Pos (5U)
5743#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
5744#define FMC_SR_IFEN FMC_SR_IFEN_Msk
5745#define FMC_SR_FEMPT_Pos (6U)
5746#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
5747#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
5749/****************** Bit definition for FMC_PMEM register ******************/
5750#define FMC_PMEM_MEMSET_Pos (0U)
5751#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
5752#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
5753#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
5754#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
5755#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
5756#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
5757#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
5758#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
5759#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
5760#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
5762#define FMC_PMEM_MEMWAIT_Pos (8U)
5763#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
5764#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
5765#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
5766#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
5767#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
5768#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
5769#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
5770#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
5771#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
5772#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
5774#define FMC_PMEM_MEMHOLD_Pos (16U)
5775#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
5776#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
5777#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
5778#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
5779#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
5780#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
5781#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
5782#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
5783#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
5784#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
5786#define FMC_PMEM_MEMHIZ_Pos (24U)
5787#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
5788#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
5789#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
5790#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
5791#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
5792#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
5793#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
5794#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
5795#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
5796#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
5798/****************** Bit definition for FMC_PATT register *******************/
5799#define FMC_PATT_ATTSET_Pos (0U)
5800#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
5801#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
5802#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
5803#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
5804#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
5805#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
5806#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
5807#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
5808#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
5809#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
5811#define FMC_PATT_ATTWAIT_Pos (8U)
5812#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
5813#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
5814#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
5815#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
5816#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
5817#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
5818#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
5819#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
5820#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
5821#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
5823#define FMC_PATT_ATTHOLD_Pos (16U)
5824#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
5825#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
5826#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
5827#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
5828#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
5829#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
5830#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
5831#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
5832#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
5833#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
5835#define FMC_PATT_ATTHIZ_Pos (24U)
5836#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
5837#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
5838#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
5839#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
5840#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
5841#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
5842#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
5843#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
5844#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
5845#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
5847/****************** Bit definition for FMC_ECCR register *******************/
5848#define FMC_ECCR_ECC_Pos (0U)
5849#define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)
5850#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk
5852/******************************************************************************/
5853/* */
5854/* General Purpose IOs (GPIO) */
5855/* */
5856/******************************************************************************/
5857/****************** Bits definition for GPIO_MODER register *****************/
5858#define GPIO_MODER_MODE0_Pos (0U)
5859#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
5860#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
5861#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
5862#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
5863#define GPIO_MODER_MODE1_Pos (2U)
5864#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
5865#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
5866#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
5867#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
5868#define GPIO_MODER_MODE2_Pos (4U)
5869#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
5870#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
5871#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
5872#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
5873#define GPIO_MODER_MODE3_Pos (6U)
5874#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
5875#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
5876#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
5877#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
5878#define GPIO_MODER_MODE4_Pos (8U)
5879#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
5880#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
5881#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
5882#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
5883#define GPIO_MODER_MODE5_Pos (10U)
5884#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
5885#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
5886#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
5887#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
5888#define GPIO_MODER_MODE6_Pos (12U)
5889#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
5890#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
5891#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
5892#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
5893#define GPIO_MODER_MODE7_Pos (14U)
5894#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
5895#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
5896#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
5897#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
5898#define GPIO_MODER_MODE8_Pos (16U)
5899#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
5900#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
5901#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
5902#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
5903#define GPIO_MODER_MODE9_Pos (18U)
5904#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
5905#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
5906#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
5907#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
5908#define GPIO_MODER_MODE10_Pos (20U)
5909#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
5910#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
5911#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
5912#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
5913#define GPIO_MODER_MODE11_Pos (22U)
5914#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
5915#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
5916#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
5917#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
5918#define GPIO_MODER_MODE12_Pos (24U)
5919#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
5920#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
5921#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
5922#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
5923#define GPIO_MODER_MODE13_Pos (26U)
5924#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
5925#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
5926#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
5927#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
5928#define GPIO_MODER_MODE14_Pos (28U)
5929#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
5930#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
5931#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
5932#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
5933#define GPIO_MODER_MODE15_Pos (30U)
5934#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
5935#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
5936#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
5937#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
5939/* Legacy defines */
5940#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
5941#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
5942#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
5943#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
5944#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
5945#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
5946#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
5947#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
5948#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
5949#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
5950#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
5951#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
5952#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
5953#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
5954#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
5955#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
5956#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
5957#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
5958#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
5959#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
5960#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
5961#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
5962#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
5963#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
5964#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
5965#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
5966#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
5967#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
5968#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
5969#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
5970#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
5971#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
5972#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
5973#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
5974#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
5975#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
5976#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
5977#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
5978#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
5979#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
5980#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
5981#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
5982#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
5983#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
5984#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
5985#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
5986#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
5987#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
5988
5989/****************** Bits definition for GPIO_OTYPER register ****************/
5990#define GPIO_OTYPER_OT0_Pos (0U)
5991#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
5992#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
5993#define GPIO_OTYPER_OT1_Pos (1U)
5994#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
5995#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
5996#define GPIO_OTYPER_OT2_Pos (2U)
5997#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
5998#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
5999#define GPIO_OTYPER_OT3_Pos (3U)
6000#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
6001#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
6002#define GPIO_OTYPER_OT4_Pos (4U)
6003#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
6004#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
6005#define GPIO_OTYPER_OT5_Pos (5U)
6006#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
6007#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
6008#define GPIO_OTYPER_OT6_Pos (6U)
6009#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
6010#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
6011#define GPIO_OTYPER_OT7_Pos (7U)
6012#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
6013#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
6014#define GPIO_OTYPER_OT8_Pos (8U)
6015#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
6016#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
6017#define GPIO_OTYPER_OT9_Pos (9U)
6018#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
6019#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
6020#define GPIO_OTYPER_OT10_Pos (10U)
6021#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
6022#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
6023#define GPIO_OTYPER_OT11_Pos (11U)
6024#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
6025#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
6026#define GPIO_OTYPER_OT12_Pos (12U)
6027#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
6028#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
6029#define GPIO_OTYPER_OT13_Pos (13U)
6030#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
6031#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
6032#define GPIO_OTYPER_OT14_Pos (14U)
6033#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
6034#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
6035#define GPIO_OTYPER_OT15_Pos (15U)
6036#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
6037#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
6038
6039/* Legacy defines */
6040#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
6041#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
6042#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
6043#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
6044#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
6045#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
6046#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
6047#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
6048#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
6049#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
6050#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
6051#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
6052#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
6053#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
6054#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
6055#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
6056
6057/****************** Bits definition for GPIO_OSPEEDR register ***************/
6058#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
6059#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
6060#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
6061#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
6062#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
6063#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
6064#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
6065#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
6066#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
6067#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
6068#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
6069#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
6070#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
6071#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
6072#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
6073#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
6074#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
6075#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
6076#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
6077#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
6078#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
6079#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
6080#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
6081#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
6082#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
6083#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
6084#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
6085#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
6086#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
6087#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
6088#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
6089#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
6090#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
6091#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
6092#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
6093#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
6094#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
6095#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
6096#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
6097#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
6098#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
6099#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
6100#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
6101#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
6102#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
6103#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
6104#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
6105#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
6106#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
6107#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
6108#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
6109#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
6110#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
6111#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
6112#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
6113#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
6114#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
6115#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
6116#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
6117#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
6118#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
6119#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
6120#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
6121#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
6122#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
6123#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
6124#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
6125#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
6126#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
6127#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
6128#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
6129#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
6130#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
6131#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
6132#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
6133#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
6134#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
6135#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
6136#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
6137#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
6139/* Legacy defines */
6140#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
6141#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
6142#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
6143#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
6144#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
6145#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
6146#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
6147#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
6148#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
6149#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
6150#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
6151#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
6152#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
6153#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
6154#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
6155#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
6156#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
6157#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
6158#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
6159#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
6160#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
6161#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
6162#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
6163#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
6164#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
6165#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
6166#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
6167#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
6168#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
6169#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
6170#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
6171#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
6172#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
6173#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
6174#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
6175#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
6176#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
6177#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
6178#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
6179#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
6180#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
6181#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
6182#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
6183#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
6184#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
6185#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
6186#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
6187#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
6188
6189/****************** Bits definition for GPIO_PUPDR register *****************/
6190#define GPIO_PUPDR_PUPD0_Pos (0U)
6191#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
6192#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
6193#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
6194#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
6195#define GPIO_PUPDR_PUPD1_Pos (2U)
6196#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
6197#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
6198#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
6199#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
6200#define GPIO_PUPDR_PUPD2_Pos (4U)
6201#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
6202#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
6203#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
6204#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
6205#define GPIO_PUPDR_PUPD3_Pos (6U)
6206#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
6207#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
6208#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
6209#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
6210#define GPIO_PUPDR_PUPD4_Pos (8U)
6211#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
6212#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
6213#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
6214#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
6215#define GPIO_PUPDR_PUPD5_Pos (10U)
6216#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
6217#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
6218#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
6219#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
6220#define GPIO_PUPDR_PUPD6_Pos (12U)
6221#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
6222#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
6223#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
6224#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
6225#define GPIO_PUPDR_PUPD7_Pos (14U)
6226#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
6227#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
6228#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
6229#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
6230#define GPIO_PUPDR_PUPD8_Pos (16U)
6231#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
6232#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
6233#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
6234#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
6235#define GPIO_PUPDR_PUPD9_Pos (18U)
6236#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
6237#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
6238#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
6239#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
6240#define GPIO_PUPDR_PUPD10_Pos (20U)
6241#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
6242#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
6243#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
6244#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
6245#define GPIO_PUPDR_PUPD11_Pos (22U)
6246#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
6247#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
6248#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
6249#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
6250#define GPIO_PUPDR_PUPD12_Pos (24U)
6251#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
6252#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
6253#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
6254#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
6255#define GPIO_PUPDR_PUPD13_Pos (26U)
6256#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
6257#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
6258#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
6259#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
6260#define GPIO_PUPDR_PUPD14_Pos (28U)
6261#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
6262#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
6263#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
6264#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
6265#define GPIO_PUPDR_PUPD15_Pos (30U)
6266#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
6267#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
6268#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
6269#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
6271/* Legacy defines */
6272#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
6273#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
6274#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
6275#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
6276#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
6277#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
6278#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
6279#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
6280#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
6281#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
6282#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
6283#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
6284#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
6285#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
6286#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
6287#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
6288#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
6289#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
6290#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
6291#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
6292#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
6293#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
6294#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
6295#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
6296#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
6297#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
6298#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
6299#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
6300#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
6301#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
6302#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
6303#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
6304#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
6305#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
6306#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
6307#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
6308#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
6309#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
6310#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
6311#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
6312#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
6313#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
6314#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
6315#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
6316#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
6317#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
6318#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
6319#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
6320
6321/****************** Bits definition for GPIO_IDR register *******************/
6322#define GPIO_IDR_ID0_Pos (0U)
6323#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
6324#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
6325#define GPIO_IDR_ID1_Pos (1U)
6326#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
6327#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
6328#define GPIO_IDR_ID2_Pos (2U)
6329#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
6330#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
6331#define GPIO_IDR_ID3_Pos (3U)
6332#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
6333#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
6334#define GPIO_IDR_ID4_Pos (4U)
6335#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
6336#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
6337#define GPIO_IDR_ID5_Pos (5U)
6338#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
6339#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
6340#define GPIO_IDR_ID6_Pos (6U)
6341#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
6342#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
6343#define GPIO_IDR_ID7_Pos (7U)
6344#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
6345#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
6346#define GPIO_IDR_ID8_Pos (8U)
6347#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
6348#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
6349#define GPIO_IDR_ID9_Pos (9U)
6350#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
6351#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
6352#define GPIO_IDR_ID10_Pos (10U)
6353#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
6354#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
6355#define GPIO_IDR_ID11_Pos (11U)
6356#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
6357#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
6358#define GPIO_IDR_ID12_Pos (12U)
6359#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
6360#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
6361#define GPIO_IDR_ID13_Pos (13U)
6362#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
6363#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
6364#define GPIO_IDR_ID14_Pos (14U)
6365#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
6366#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
6367#define GPIO_IDR_ID15_Pos (15U)
6368#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
6369#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
6370
6371/* Legacy defines */
6372#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
6373#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
6374#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
6375#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
6376#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
6377#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
6378#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
6379#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
6380#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
6381#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
6382#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
6383#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
6384#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
6385#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
6386#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
6387#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
6388
6389/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
6390#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
6391#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
6392#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
6393#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
6394#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
6395#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
6396#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
6397#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
6398#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
6399#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
6400#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
6401#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
6402#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
6403#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
6404#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
6405#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
6406
6407/****************** Bits definition for GPIO_ODR register *******************/
6408#define GPIO_ODR_OD0_Pos (0U)
6409#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
6410#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
6411#define GPIO_ODR_OD1_Pos (1U)
6412#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
6413#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
6414#define GPIO_ODR_OD2_Pos (2U)
6415#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
6416#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
6417#define GPIO_ODR_OD3_Pos (3U)
6418#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
6419#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
6420#define GPIO_ODR_OD4_Pos (4U)
6421#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
6422#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
6423#define GPIO_ODR_OD5_Pos (5U)
6424#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
6425#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
6426#define GPIO_ODR_OD6_Pos (6U)
6427#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
6428#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
6429#define GPIO_ODR_OD7_Pos (7U)
6430#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
6431#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
6432#define GPIO_ODR_OD8_Pos (8U)
6433#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
6434#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
6435#define GPIO_ODR_OD9_Pos (9U)
6436#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
6437#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
6438#define GPIO_ODR_OD10_Pos (10U)
6439#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
6440#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
6441#define GPIO_ODR_OD11_Pos (11U)
6442#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
6443#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
6444#define GPIO_ODR_OD12_Pos (12U)
6445#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
6446#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
6447#define GPIO_ODR_OD13_Pos (13U)
6448#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
6449#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
6450#define GPIO_ODR_OD14_Pos (14U)
6451#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
6452#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
6453#define GPIO_ODR_OD15_Pos (15U)
6454#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
6455#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
6456
6457/* Legacy defines */
6458#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
6459#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
6460#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
6461#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
6462#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
6463#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
6464#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
6465#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
6466#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
6467#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
6468#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
6469#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
6470#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
6471#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
6472#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
6473#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
6474
6475/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6476#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
6477#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
6478#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
6479#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
6480#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
6481#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
6482#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
6483#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
6484#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
6485#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
6486#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
6487#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
6488#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
6489#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
6490#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
6491#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
6492
6493/****************** Bits definition for GPIO_BSRR register ******************/
6494#define GPIO_BSRR_BS0_Pos (0U)
6495#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
6496#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
6497#define GPIO_BSRR_BS1_Pos (1U)
6498#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
6499#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
6500#define GPIO_BSRR_BS2_Pos (2U)
6501#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
6502#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
6503#define GPIO_BSRR_BS3_Pos (3U)
6504#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
6505#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
6506#define GPIO_BSRR_BS4_Pos (4U)
6507#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
6508#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
6509#define GPIO_BSRR_BS5_Pos (5U)
6510#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
6511#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
6512#define GPIO_BSRR_BS6_Pos (6U)
6513#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
6514#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
6515#define GPIO_BSRR_BS7_Pos (7U)
6516#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
6517#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
6518#define GPIO_BSRR_BS8_Pos (8U)
6519#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
6520#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
6521#define GPIO_BSRR_BS9_Pos (9U)
6522#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
6523#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
6524#define GPIO_BSRR_BS10_Pos (10U)
6525#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
6526#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
6527#define GPIO_BSRR_BS11_Pos (11U)
6528#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
6529#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
6530#define GPIO_BSRR_BS12_Pos (12U)
6531#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
6532#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
6533#define GPIO_BSRR_BS13_Pos (13U)
6534#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
6535#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
6536#define GPIO_BSRR_BS14_Pos (14U)
6537#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
6538#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
6539#define GPIO_BSRR_BS15_Pos (15U)
6540#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
6541#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
6542#define GPIO_BSRR_BR0_Pos (16U)
6543#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
6544#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
6545#define GPIO_BSRR_BR1_Pos (17U)
6546#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
6547#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
6548#define GPIO_BSRR_BR2_Pos (18U)
6549#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
6550#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
6551#define GPIO_BSRR_BR3_Pos (19U)
6552#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
6553#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
6554#define GPIO_BSRR_BR4_Pos (20U)
6555#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
6556#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
6557#define GPIO_BSRR_BR5_Pos (21U)
6558#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
6559#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
6560#define GPIO_BSRR_BR6_Pos (22U)
6561#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
6562#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
6563#define GPIO_BSRR_BR7_Pos (23U)
6564#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
6565#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
6566#define GPIO_BSRR_BR8_Pos (24U)
6567#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
6568#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
6569#define GPIO_BSRR_BR9_Pos (25U)
6570#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
6571#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
6572#define GPIO_BSRR_BR10_Pos (26U)
6573#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
6574#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
6575#define GPIO_BSRR_BR11_Pos (27U)
6576#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
6577#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
6578#define GPIO_BSRR_BR12_Pos (28U)
6579#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
6580#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
6581#define GPIO_BSRR_BR13_Pos (29U)
6582#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
6583#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
6584#define GPIO_BSRR_BR14_Pos (30U)
6585#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
6586#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
6587#define GPIO_BSRR_BR15_Pos (31U)
6588#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
6589#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
6590
6591/* Legacy defines */
6592#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
6593#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
6594#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
6595#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
6596#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
6597#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
6598#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
6599#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
6600#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
6601#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
6602#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
6603#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
6604#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
6605#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
6606#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
6607#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
6608#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
6609#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
6610#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
6611#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
6612#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
6613#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
6614#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
6615#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
6616#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
6617#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
6618#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
6619#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
6620#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
6621#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
6622#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
6623#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
6624
6625/****************** Bit definition for GPIO_LCKR register *********************/
6626#define GPIO_LCKR_LCK0_Pos (0U)
6627#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
6628#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
6629#define GPIO_LCKR_LCK1_Pos (1U)
6630#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
6631#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
6632#define GPIO_LCKR_LCK2_Pos (2U)
6633#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
6634#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
6635#define GPIO_LCKR_LCK3_Pos (3U)
6636#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
6637#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
6638#define GPIO_LCKR_LCK4_Pos (4U)
6639#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
6640#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
6641#define GPIO_LCKR_LCK5_Pos (5U)
6642#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
6643#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
6644#define GPIO_LCKR_LCK6_Pos (6U)
6645#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
6646#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
6647#define GPIO_LCKR_LCK7_Pos (7U)
6648#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
6649#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
6650#define GPIO_LCKR_LCK8_Pos (8U)
6651#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
6652#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
6653#define GPIO_LCKR_LCK9_Pos (9U)
6654#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
6655#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
6656#define GPIO_LCKR_LCK10_Pos (10U)
6657#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
6658#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
6659#define GPIO_LCKR_LCK11_Pos (11U)
6660#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
6661#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
6662#define GPIO_LCKR_LCK12_Pos (12U)
6663#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
6664#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
6665#define GPIO_LCKR_LCK13_Pos (13U)
6666#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
6667#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
6668#define GPIO_LCKR_LCK14_Pos (14U)
6669#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
6670#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
6671#define GPIO_LCKR_LCK15_Pos (15U)
6672#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
6673#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
6674#define GPIO_LCKR_LCKK_Pos (16U)
6675#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
6676#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
6677
6678/****************** Bit definition for GPIO_AFRL register *********************/
6679#define GPIO_AFRL_AFSEL0_Pos (0U)
6680#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
6681#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
6682#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
6683#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
6684#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
6685#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
6686#define GPIO_AFRL_AFSEL1_Pos (4U)
6687#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
6688#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
6689#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
6690#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
6691#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
6692#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
6693#define GPIO_AFRL_AFSEL2_Pos (8U)
6694#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
6695#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
6696#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
6697#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
6698#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
6699#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
6700#define GPIO_AFRL_AFSEL3_Pos (12U)
6701#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
6702#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
6703#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
6704#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
6705#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
6706#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
6707#define GPIO_AFRL_AFSEL4_Pos (16U)
6708#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
6709#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
6710#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
6711#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
6712#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
6713#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
6714#define GPIO_AFRL_AFSEL5_Pos (20U)
6715#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
6716#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
6717#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
6718#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
6719#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
6720#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
6721#define GPIO_AFRL_AFSEL6_Pos (24U)
6722#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
6723#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
6724#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
6725#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
6726#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
6727#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
6728#define GPIO_AFRL_AFSEL7_Pos (28U)
6729#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
6730#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
6731#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
6732#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
6733#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
6734#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
6736/* Legacy defines */
6737#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
6738#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
6739#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
6740#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
6741#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
6742#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
6743#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
6744#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
6745
6746/****************** Bit definition for GPIO_AFRH register *********************/
6747#define GPIO_AFRH_AFSEL8_Pos (0U)
6748#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
6749#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
6750#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
6751#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
6752#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
6753#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
6754#define GPIO_AFRH_AFSEL9_Pos (4U)
6755#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
6756#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
6757#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
6758#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
6759#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
6760#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
6761#define GPIO_AFRH_AFSEL10_Pos (8U)
6762#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
6763#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
6764#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
6765#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
6766#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
6767#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
6768#define GPIO_AFRH_AFSEL11_Pos (12U)
6769#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
6770#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
6771#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
6772#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
6773#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
6774#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
6775#define GPIO_AFRH_AFSEL12_Pos (16U)
6776#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
6777#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
6778#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
6779#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
6780#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
6781#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
6782#define GPIO_AFRH_AFSEL13_Pos (20U)
6783#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
6784#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
6785#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
6786#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
6787#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
6788#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
6789#define GPIO_AFRH_AFSEL14_Pos (24U)
6790#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
6791#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
6792#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
6793#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
6794#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
6795#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
6796#define GPIO_AFRH_AFSEL15_Pos (28U)
6797#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
6798#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
6799#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
6800#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
6801#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
6802#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
6804/* Legacy defines */
6805#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
6806#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
6807#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
6808#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
6809#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
6810#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
6811#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
6812#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
6813
6814/****************** Bits definition for GPIO_BRR register ******************/
6815#define GPIO_BRR_BR0_Pos (0U)
6816#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)
6817#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
6818#define GPIO_BRR_BR1_Pos (1U)
6819#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)
6820#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
6821#define GPIO_BRR_BR2_Pos (2U)
6822#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)
6823#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
6824#define GPIO_BRR_BR3_Pos (3U)
6825#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)
6826#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
6827#define GPIO_BRR_BR4_Pos (4U)
6828#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)
6829#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
6830#define GPIO_BRR_BR5_Pos (5U)
6831#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)
6832#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
6833#define GPIO_BRR_BR6_Pos (6U)
6834#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)
6835#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
6836#define GPIO_BRR_BR7_Pos (7U)
6837#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)
6838#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
6839#define GPIO_BRR_BR8_Pos (8U)
6840#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)
6841#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
6842#define GPIO_BRR_BR9_Pos (9U)
6843#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)
6844#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
6845#define GPIO_BRR_BR10_Pos (10U)
6846#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)
6847#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
6848#define GPIO_BRR_BR11_Pos (11U)
6849#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)
6850#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
6851#define GPIO_BRR_BR12_Pos (12U)
6852#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)
6853#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
6854#define GPIO_BRR_BR13_Pos (13U)
6855#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)
6856#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
6857#define GPIO_BRR_BR14_Pos (14U)
6858#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)
6859#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
6860#define GPIO_BRR_BR15_Pos (15U)
6861#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)
6862#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
6863
6864/* Legacy defines */
6865#define GPIO_BRR_BR_0 GPIO_BRR_BR0
6866#define GPIO_BRR_BR_1 GPIO_BRR_BR1
6867#define GPIO_BRR_BR_2 GPIO_BRR_BR2
6868#define GPIO_BRR_BR_3 GPIO_BRR_BR3
6869#define GPIO_BRR_BR_4 GPIO_BRR_BR4
6870#define GPIO_BRR_BR_5 GPIO_BRR_BR5
6871#define GPIO_BRR_BR_6 GPIO_BRR_BR6
6872#define GPIO_BRR_BR_7 GPIO_BRR_BR7
6873#define GPIO_BRR_BR_8 GPIO_BRR_BR8
6874#define GPIO_BRR_BR_9 GPIO_BRR_BR9
6875#define GPIO_BRR_BR_10 GPIO_BRR_BR10
6876#define GPIO_BRR_BR_11 GPIO_BRR_BR11
6877#define GPIO_BRR_BR_12 GPIO_BRR_BR12
6878#define GPIO_BRR_BR_13 GPIO_BRR_BR13
6879#define GPIO_BRR_BR_14 GPIO_BRR_BR14
6880#define GPIO_BRR_BR_15 GPIO_BRR_BR15
6881
6882/******************************************************************************/
6883/* */
6884/* High Resolution Timer (HRTIM) */
6885/* */
6886/******************************************************************************/
6887/******************** Master Timer control register ***************************/
6888#define HRTIM_MCR_CK_PSC_Pos (0U)
6889#define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos)
6890#define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk
6891#define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos)
6892#define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos)
6893#define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos)
6894#define HRTIM_MCR_CONT_Pos (3U)
6895#define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos)
6896#define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk
6897#define HRTIM_MCR_RETRIG_Pos (4U)
6898#define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos)
6899#define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk
6900#define HRTIM_MCR_HALF_Pos (5U)
6901#define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos)
6902#define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk
6903#define HRTIM_MCR_INTLVD_Pos (6U)
6904#define HRTIM_MCR_INTLVD_Msk (0x3UL << HRTIM_MCR_INTLVD_Pos)
6905#define HRTIM_MCR_INTLVD HRTIM_MCR_INTLVD_Msk
6906#define HRTIM_MCR_INTLVD_0 (0x1UL << HRTIM_MCR_INTLVD_Pos)
6907#define HRTIM_MCR_INTLVD_1 (0x2UL << HRTIM_MCR_INTLVD_Pos)
6908#define HRTIM_MCR_SYNC_IN_Pos (8U)
6909#define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos)
6910#define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk
6911#define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos)
6912#define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos)
6913#define HRTIM_MCR_SYNCRSTM_Pos (10U)
6914#define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)
6915#define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk
6916#define HRTIM_MCR_SYNCSTRTM_Pos (11U)
6917#define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)
6918#define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk
6919#define HRTIM_MCR_SYNC_OUT_Pos (12U)
6920#define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)
6921#define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk
6922#define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)
6923#define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)
6924#define HRTIM_MCR_SYNC_SRC_Pos (14U)
6925#define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)
6926#define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk
6927#define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)
6928#define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)
6929#define HRTIM_MCR_MCEN_Pos (16U)
6930#define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos)
6931#define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk
6932#define HRTIM_MCR_TACEN_Pos (17U)
6933#define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos)
6934#define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk
6935#define HRTIM_MCR_TBCEN_Pos (18U)
6936#define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos)
6937#define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk
6938#define HRTIM_MCR_TCCEN_Pos (19U)
6939#define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos)
6940#define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk
6941#define HRTIM_MCR_TDCEN_Pos (20U)
6942#define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos)
6943#define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk
6944#define HRTIM_MCR_TECEN_Pos (21U)
6945#define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos)
6946#define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk
6947#define HRTIM_MCR_TFCEN_Pos (22U)
6948#define HRTIM_MCR_TFCEN_Msk (0x1UL << HRTIM_MCR_TFCEN_Pos)
6949#define HRTIM_MCR_TFCEN HRTIM_MCR_TFCEN_Msk
6950#define HRTIM_MCR_DACSYNC_Pos (25U)
6951#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos)
6952#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk
6953#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos)
6954#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos)
6955#define HRTIM_MCR_PREEN_Pos (27U)
6956#define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos)
6957#define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk
6958#define HRTIM_MCR_MREPU_Pos (29U)
6959#define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos)
6960#define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk
6961#define HRTIM_MCR_BRSTDMA_Pos (30U)
6962#define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos)
6963#define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk
6964#define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos)
6965#define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos)
6967/******************** Master Timer Interrupt status register ******************/
6968#define HRTIM_MISR_MCMP1_Pos (0U)
6969#define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos)
6970#define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk
6971#define HRTIM_MISR_MCMP2_Pos (1U)
6972#define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos)
6973#define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk
6974#define HRTIM_MISR_MCMP3_Pos (2U)
6975#define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos)
6976#define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk
6977#define HRTIM_MISR_MCMP4_Pos (3U)
6978#define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos)
6979#define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk
6980#define HRTIM_MISR_MREP_Pos (4U)
6981#define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos)
6982#define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk
6983#define HRTIM_MISR_SYNC_Pos (5U)
6984#define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos)
6985#define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk
6986#define HRTIM_MISR_MUPD_Pos (6U)
6987#define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos)
6988#define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk
6990/******************** Master Timer Interrupt clear register *******************/
6991#define HRTIM_MICR_MCMP1_Pos (0U)
6992#define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos)
6993#define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk
6994#define HRTIM_MICR_MCMP2_Pos (1U)
6995#define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos)
6996#define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk
6997#define HRTIM_MICR_MCMP3_Pos (2U)
6998#define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos)
6999#define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk
7000#define HRTIM_MICR_MCMP4_Pos (3U)
7001#define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos)
7002#define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk
7003#define HRTIM_MICR_MREP_Pos (4U)
7004#define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos)
7005#define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk
7006#define HRTIM_MICR_SYNC_Pos (5U)
7007#define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos)
7008#define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk
7009#define HRTIM_MICR_MUPD_Pos (6U)
7010#define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos)
7011#define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk
7013/******************** Master Timer DMA/Interrupt enable register **************/
7014#define HRTIM_MDIER_MCMP1IE_Pos (0U)
7015#define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)
7016#define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk
7017#define HRTIM_MDIER_MCMP2IE_Pos (1U)
7018#define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)
7019#define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk
7020#define HRTIM_MDIER_MCMP3IE_Pos (2U)
7021#define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)
7022#define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk
7023#define HRTIM_MDIER_MCMP4IE_Pos (3U)
7024#define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)
7025#define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk
7026#define HRTIM_MDIER_MREPIE_Pos (4U)
7027#define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos)
7028#define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk
7029#define HRTIM_MDIER_SYNCIE_Pos (5U)
7030#define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos)
7031#define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk
7032#define HRTIM_MDIER_MUPDIE_Pos (6U)
7033#define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos)
7034#define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk
7035#define HRTIM_MDIER_MCMP1DE_Pos (16U)
7036#define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)
7037#define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk
7038#define HRTIM_MDIER_MCMP2DE_Pos (17U)
7039#define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)
7040#define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk
7041#define HRTIM_MDIER_MCMP3DE_Pos (18U)
7042#define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)
7043#define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk
7044#define HRTIM_MDIER_MCMP4DE_Pos (19U)
7045#define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)
7046#define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk
7047#define HRTIM_MDIER_MREPDE_Pos (20U)
7048#define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos)
7049#define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk
7050#define HRTIM_MDIER_SYNCDE_Pos (21U)
7051#define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos)
7052#define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk
7053#define HRTIM_MDIER_MUPDDE_Pos (22U)
7054#define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos)
7055#define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk
7057/******************* Bit definition for HRTIM_MCNTR register ****************/
7058#define HRTIM_MCNTR_MCNTR_Pos (0U)
7059#define HRTIM_MCNTR_MCNTR_Msk (0x0000FFFFUL << HRTIM_MCNTR_MCNTR_Pos)
7060#define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk
7062/******************* Bit definition for HRTIM_MPER register *****************/
7063#define HRTIM_MPER_MPER_Pos (0U)
7064#define HRTIM_MPER_MPER_Msk (0x0000FFFFUL << HRTIM_MPER_MPER_Pos)
7065#define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk
7067/******************* Bit definition for HRTIM_MREP register *****************/
7068#define HRTIM_MREP_MREP_Pos (0U)
7069#define HRTIM_MREP_MREP_Msk (0x000000FFUL << HRTIM_MREP_MREP_Pos)
7070#define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk
7072/******************* Bit definition for HRTIM_MCMP1R register *****************/
7073#define HRTIM_MCMP1R_MCMP1R_Pos (0U)
7074#define HRTIM_MCMP1R_MCMP1R_Msk (0x0000FFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)
7075#define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk
7077/******************* Bit definition for HRTIM_MCMP2R register *****************/
7078#define HRTIM_MCMP2R_MCMP2R_Pos (0U)
7079#define HRTIM_MCMP2R_MCMP2R_Msk (0x0000FFFFUL << HRTIM_MCMP2R_MCMP2R_Pos)
7080#define HRTIM_MCMP2R_MCMP2R HRTIM_MCMP2R_MCMP2R_Msk
7082/******************* Bit definition for HRTIM_MCMP3R register *****************/
7083#define HRTIM_MCMP3R_MCMP3R_Pos (0U)
7084#define HRTIM_MCMP3R_MCMP3R_Msk (0x0000FFFFUL << HRTIM_MCMP3R_MCMP3R_Pos)
7085#define HRTIM_MCMP3R_MCMP3R HRTIM_MCMP3R_MCMP3R_Msk
7087/******************* Bit definition for HRTIM_MCMP4R register *****************/
7088#define HRTIM_MCMP4R_MCMP4R_Pos (0U)
7089#define HRTIM_MCMP4R_MCMP4R_Msk (0x0000FFFFUL << HRTIM_MCMP4R_MCMP4R_Pos)
7090#define HRTIM_MCMP4R_MCMP4R HRTIM_MCMP4R_MCMP4R_Msk
7092/* Legacy defines */
7093#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
7094#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
7095#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
7096
7097/******************** Slave control register **********************************/
7098#define HRTIM_TIMCR_CK_PSC_Pos (0U)
7099#define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)
7100#define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk
7101#define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)
7102#define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)
7103#define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)
7104#define HRTIM_TIMCR_CONT_Pos (3U)
7105#define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos)
7106#define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk
7107#define HRTIM_TIMCR_RETRIG_Pos (4U)
7108#define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos)
7109#define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk
7110#define HRTIM_TIMCR_HALF_Pos (5U)
7111#define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos)
7112#define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk
7113#define HRTIM_TIMCR_PSHPLL_Pos (6U)
7114#define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)
7115#define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk
7116#define HRTIM_TIMCR_INTLVD_Pos (7U)
7117#define HRTIM_TIMCR_INTLVD_Msk (0x3UL << HRTIM_TIMCR_INTLVD_Pos)
7118#define HRTIM_TIMCR_INTLVD HRTIM_TIMCR_INTLVD_Msk
7119#define HRTIM_TIMCR_INTLVD_0 (0x1UL << HRTIM_TIMCR_INTLVD_Pos)
7120#define HRTIM_TIMCR_INTLVD_1 (0x2UL << HRTIM_TIMCR_INTLVD_Pos)
7121#define HRTIM_TIMCR_RSYNCU_Pos (9U)
7122#define HRTIM_TIMCR_RSYNCU_Msk (0x1UL << HRTIM_TIMCR_RSYNCU_Pos)
7123#define HRTIM_TIMCR_RSYNCU HRTIM_TIMCR_RSYNCU_Msk
7124#define HRTIM_TIMCR_SYNCRST_Pos (10U)
7125#define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)
7126#define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk
7127#define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
7128#define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)
7129#define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk
7130#define HRTIM_TIMCR_DELCMP2_Pos (12U)
7131#define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)
7132#define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk
7133#define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)
7134#define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)
7135#define HRTIM_TIMCR_DELCMP4_Pos (14U)
7136#define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)
7137#define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk
7138#define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)
7139#define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)
7140#define HRTIM_TIMCR_TFU_Pos (16U)
7141#define HRTIM_TIMCR_TFU_Msk (0x1UL << HRTIM_TIMCR_TFU_Pos)
7142#define HRTIM_TIMCR_TFU HRTIM_TIMCR_TFU_Msk
7143#define HRTIM_TIMCR_TREPU_Pos (17U)
7144#define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos)
7145#define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk
7146#define HRTIM_TIMCR_TRSTU_Pos (18U)
7147#define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos)
7148#define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk
7149#define HRTIM_TIMCR_TAU_Pos (19U)
7150#define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos)
7151#define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk
7152#define HRTIM_TIMCR_TBU_Pos (20U)
7153#define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos)
7154#define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk
7155#define HRTIM_TIMCR_TCU_Pos (21U)
7156#define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos)
7157#define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk
7158#define HRTIM_TIMCR_TDU_Pos (22U)
7159#define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos)
7160#define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk
7161#define HRTIM_TIMCR_TEU_Pos (23U)
7162#define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos)
7163#define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk
7164#define HRTIM_TIMCR_MSTU_Pos (24U)
7165#define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos)
7166#define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk
7167#define HRTIM_TIMCR_DACSYNC_Pos (25U)
7168#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)
7169#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk
7170#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)
7171#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)
7172#define HRTIM_TIMCR_PREEN_Pos (27U)
7173#define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos)
7174#define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk
7175#define HRTIM_TIMCR_UPDGAT_Pos (28U)
7176#define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)
7177#define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk
7178#define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)
7179#define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)
7180#define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)
7181#define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)
7183/******************** Slave Interrupt status register **************************/
7184#define HRTIM_TIMISR_CMP1_Pos (0U)
7185#define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos)
7186#define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk
7187#define HRTIM_TIMISR_CMP2_Pos (1U)
7188#define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos)
7189#define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk
7190#define HRTIM_TIMISR_CMP3_Pos (2U)
7191#define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos)
7192#define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk
7193#define HRTIM_TIMISR_CMP4_Pos (3U)
7194#define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos)
7195#define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk
7196#define HRTIM_TIMISR_REP_Pos (4U)
7197#define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos)
7198#define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk
7199#define HRTIM_TIMISR_UPD_Pos (6U)
7200#define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos)
7201#define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk
7202#define HRTIM_TIMISR_CPT1_Pos (7U)
7203#define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos)
7204#define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk
7205#define HRTIM_TIMISR_CPT2_Pos (8U)
7206#define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos)
7207#define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk
7208#define HRTIM_TIMISR_SET1_Pos (9U)
7209#define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos)
7210#define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk
7211#define HRTIM_TIMISR_RST1_Pos (10U)
7212#define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos)
7213#define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk
7214#define HRTIM_TIMISR_SET2_Pos (11U)
7215#define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos)
7216#define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk
7217#define HRTIM_TIMISR_RST2_Pos (12U)
7218#define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos)
7219#define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk
7220#define HRTIM_TIMISR_RST_Pos (13U)
7221#define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos)
7222#define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk
7223#define HRTIM_TIMISR_DLYPRT_Pos (14U)
7224#define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)
7225#define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk
7226#define HRTIM_TIMISR_CPPSTAT_Pos (16U)
7227#define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)
7228#define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk
7229#define HRTIM_TIMISR_IPPSTAT_Pos (17U)
7230#define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)
7231#define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk
7232#define HRTIM_TIMISR_O1STAT_Pos (18U)
7233#define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos)
7234#define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk
7235#define HRTIM_TIMISR_O2STAT_Pos (19U)
7236#define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos)
7237#define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk
7238#define HRTIM_TIMISR_O1CPY_Pos (20U)
7239#define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos)
7240#define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk
7241#define HRTIM_TIMISR_O2CPY_Pos (21U)
7242#define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos)
7243#define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk
7245/******************** Slave Interrupt clear register **************************/
7246#define HRTIM_TIMICR_CMP1C_Pos (0U)
7247#define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos)
7248#define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk
7249#define HRTIM_TIMICR_CMP2C_Pos (1U)
7250#define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos)
7251#define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk
7252#define HRTIM_TIMICR_CMP3C_Pos (2U)
7253#define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos)
7254#define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk
7255#define HRTIM_TIMICR_CMP4C_Pos (3U)
7256#define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos)
7257#define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk
7258#define HRTIM_TIMICR_REPC_Pos (4U)
7259#define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos)
7260#define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk
7261#define HRTIM_TIMICR_UPDC_Pos (6U)
7262#define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos)
7263#define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk
7264#define HRTIM_TIMICR_CPT1C_Pos (7U)
7265#define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos)
7266#define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk
7267#define HRTIM_TIMICR_CPT2C_Pos (8U)
7268#define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos)
7269#define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk
7270#define HRTIM_TIMICR_SET1C_Pos (9U)
7271#define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos)
7272#define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk
7273#define HRTIM_TIMICR_RST1C_Pos (10U)
7274#define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos)
7275#define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk
7276#define HRTIM_TIMICR_SET2C_Pos (11U)
7277#define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos)
7278#define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk
7279#define HRTIM_TIMICR_RST2C_Pos (12U)
7280#define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos)
7281#define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk
7282#define HRTIM_TIMICR_RSTC_Pos (13U)
7283#define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos)
7284#define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk
7285#define HRTIM_TIMICR_DLYPRTC_Pos (14U)
7286#define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)
7287#define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk
7289/******************** Slave DMA/Interrupt enable register *********************/
7290#define HRTIM_TIMDIER_CMP1IE_Pos (0U)
7291#define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)
7292#define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk
7293#define HRTIM_TIMDIER_CMP2IE_Pos (1U)
7294#define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)
7295#define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk
7296#define HRTIM_TIMDIER_CMP3IE_Pos (2U)
7297#define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)
7298#define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk
7299#define HRTIM_TIMDIER_CMP4IE_Pos (3U)
7300#define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)
7301#define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk
7302#define HRTIM_TIMDIER_REPIE_Pos (4U)
7303#define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos)
7304#define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk
7305#define HRTIM_TIMDIER_UPDIE_Pos (6U)
7306#define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)
7307#define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk
7308#define HRTIM_TIMDIER_CPT1IE_Pos (7U)
7309#define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)
7310#define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk
7311#define HRTIM_TIMDIER_CPT2IE_Pos (8U)
7312#define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)
7313#define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk
7314#define HRTIM_TIMDIER_SET1IE_Pos (9U)
7315#define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)
7316#define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk
7317#define HRTIM_TIMDIER_RST1IE_Pos (10U)
7318#define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)
7319#define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk
7320#define HRTIM_TIMDIER_SET2IE_Pos (11U)
7321#define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)
7322#define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk
7323#define HRTIM_TIMDIER_RST2IE_Pos (12U)
7324#define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)
7325#define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk
7326#define HRTIM_TIMDIER_RSTIE_Pos (13U)
7327#define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)
7328#define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk
7329#define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
7330#define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)
7331#define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk
7333#define HRTIM_TIMDIER_CMP1DE_Pos (16U)
7334#define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)
7335#define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk
7336#define HRTIM_TIMDIER_CMP2DE_Pos (17U)
7337#define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)
7338#define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk
7339#define HRTIM_TIMDIER_CMP3DE_Pos (18U)
7340#define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)
7341#define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk
7342#define HRTIM_TIMDIER_CMP4DE_Pos (19U)
7343#define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)
7344#define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk
7345#define HRTIM_TIMDIER_REPDE_Pos (20U)
7346#define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos)
7347#define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk
7348#define HRTIM_TIMDIER_UPDDE_Pos (22U)
7349#define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)
7350#define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk
7351#define HRTIM_TIMDIER_CPT1DE_Pos (23U)
7352#define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)
7353#define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk
7354#define HRTIM_TIMDIER_CPT2DE_Pos (24U)
7355#define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)
7356#define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk
7357#define HRTIM_TIMDIER_SET1DE_Pos (25U)
7358#define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)
7359#define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk
7360#define HRTIM_TIMDIER_RST1DE_Pos (26U)
7361#define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)
7362#define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk
7363#define HRTIM_TIMDIER_SET2DE_Pos (27U)
7364#define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)
7365#define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk
7366#define HRTIM_TIMDIER_RST2DE_Pos (28U)
7367#define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)
7368#define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk
7369#define HRTIM_TIMDIER_RSTDE_Pos (29U)
7370#define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)
7371#define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk
7372#define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
7373#define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)
7374#define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk
7376/****************** Bit definition for HRTIM_CNTR register ****************/
7377#define HRTIM_CNTR_CNTR_Pos (0U)
7378#define HRTIM_CNTR_CNTR_Msk (0x0000FFFFUL << HRTIM_CNTR_CNTR_Pos)
7379#define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk
7381/******************* Bit definition for HRTIM_PER register *****************/
7382#define HRTIM_PER_PER_Pos (0U)
7383#define HRTIM_PER_PER_Msk (0x0000FFFFUL << HRTIM_PER_PER_Pos)
7384#define HRTIM_PER_PER HRTIM_PER_PER_Msk
7386/******************* Bit definition for HRTIM_REP register *****************/
7387#define HRTIM_REP_REP_Pos (0U)
7388#define HRTIM_REP_REP_Msk (0x000000FFUL << HRTIM_REP_REP_Pos)
7389#define HRTIM_REP_REP HRTIM_REP_REP_Msk
7391/******************* Bit definition for HRTIM_CMP1R register *****************/
7392#define HRTIM_CMP1R_CMP1R_Pos (0U)
7393#define HRTIM_CMP1R_CMP1R_Msk (0x0000FFFFUL << HRTIM_CMP1R_CMP1R_Pos)
7394#define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk
7396/******************* Bit definition for HRTIM_CMP1CR register *****************/
7397#define HRTIM_CMP1CR_CMP1CR_Pos (0U)
7398#define HRTIM_CMP1CR_CMP1CR_Msk (0x0000FFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)
7399#define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk
7401/******************* Bit definition for HRTIM_CMP2R register *****************/
7402#define HRTIM_CMP2R_CMP2R_Pos (0U)
7403#define HRTIM_CMP2R_CMP2R_Msk (0x0000FFFFUL << HRTIM_CMP2R_CMP2R_Pos)
7404#define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk
7406/******************* Bit definition for HRTIM_CMP3R register *****************/
7407#define HRTIM_CMP3R_CMP3R_Pos (0U)
7408#define HRTIM_CMP3R_CMP3R_Msk (0x0000FFFFUL << HRTIM_CMP3R_CMP3R_Pos)
7409#define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk
7411/******************* Bit definition for HRTIM_CMP4R register *****************/
7412#define HRTIM_CMP4R_CMP4R_Pos (0U)
7413#define HRTIM_CMP4R_CMP4R_Msk (0x0000FFFFUL << HRTIM_CMP4R_CMP4R_Pos)
7414#define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk
7416/******************* Bit definition for HRTIM_CPT1R register ****************/
7417#define HRTIM_CPT1R_CPT1R_Pos (0U)
7418#define HRTIM_CPT1R_CPT1R_Msk (0x0000FFFFUL << HRTIM_CPT1R_CPT1R_Pos)
7419#define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk
7420#define HRTIM_CPT1R_DIR_Pos (16U)
7421#define HRTIM_CPT1R_DIR_Msk (0x1UL << HRTIM_CPT1R_DIR_Pos)
7422#define HRTIM_CPT1R_DIR HRTIM_CPT1R_DIR_Msk
7424/******************* Bit definition for HRTIM_CPT2R register ****************/
7425#define HRTIM_CPT2R_CPT2R_Pos (0U)
7426#define HRTIM_CPT2R_CPT2R_Msk (0x0000FFFFUL << HRTIM_CPT2R_CPT2R_Pos)
7427#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk
7428#define HRTIM_CPT2R_DIR_Pos (16U)
7429#define HRTIM_CPT2R_DIR_Msk (0x1UL << HRTIM_CPT2R_DIR_Pos)
7430#define HRTIM_CPT2R_DIR HRTIM_CPT2R_DIR_Msk
7432/******************** Bit definition for Slave Deadtime register **************/
7433#define HRTIM_DTR_DTR_Pos (0U)
7434#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos)
7435#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk
7436#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos)
7437#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos)
7438#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos)
7439#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos)
7440#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos)
7441#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos)
7442#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos)
7443#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos)
7444#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos)
7445#define HRTIM_DTR_SDTR_Pos (9U)
7446#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos)
7447#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk
7448#define HRTIM_DTR_DTPRSC_Pos (10U)
7449#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos)
7450#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk
7451#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos)
7452#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos)
7453#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos)
7454#define HRTIM_DTR_DTRSLK_Pos (14U)
7455#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos)
7456#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk
7457#define HRTIM_DTR_DTRLK_Pos (15U)
7458#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos)
7459#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk
7460#define HRTIM_DTR_DTF_Pos (16U)
7461#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos)
7462#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk
7463#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos)
7464#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos)
7465#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos)
7466#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos)
7467#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos)
7468#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos)
7469#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos)
7470#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos)
7471#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos)
7472#define HRTIM_DTR_SDTF_Pos (25U)
7473#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos)
7474#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk
7475#define HRTIM_DTR_DTFSLK_Pos (30U)
7476#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos)
7477#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk
7478#define HRTIM_DTR_DTFLK_Pos (31U)
7479#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos)
7480#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk
7482/**** Bit definition for Slave Output 1 set register **************************/
7483#define HRTIM_SET1R_SST_Pos (0U)
7484#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos)
7485#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk
7486#define HRTIM_SET1R_RESYNC_Pos (1U)
7487#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos)
7488#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk
7489#define HRTIM_SET1R_PER_Pos (2U)
7490#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos)
7491#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk
7492#define HRTIM_SET1R_CMP1_Pos (3U)
7493#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos)
7494#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk
7495#define HRTIM_SET1R_CMP2_Pos (4U)
7496#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos)
7497#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk
7498#define HRTIM_SET1R_CMP3_Pos (5U)
7499#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos)
7500#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk
7501#define HRTIM_SET1R_CMP4_Pos (6U)
7502#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos)
7503#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk
7505#define HRTIM_SET1R_MSTPER_Pos (7U)
7506#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos)
7507#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk
7508#define HRTIM_SET1R_MSTCMP1_Pos (8U)
7509#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)
7510#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk
7511#define HRTIM_SET1R_MSTCMP2_Pos (9U)
7512#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)
7513#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk
7514#define HRTIM_SET1R_MSTCMP3_Pos (10U)
7515#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)
7516#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk
7517#define HRTIM_SET1R_MSTCMP4_Pos (11U)
7518#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)
7519#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk
7521#define HRTIM_SET1R_TIMEVNT1_Pos (12U)
7522#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)
7523#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk
7524#define HRTIM_SET1R_TIMEVNT2_Pos (13U)
7525#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)
7526#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk
7527#define HRTIM_SET1R_TIMEVNT3_Pos (14U)
7528#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)
7529#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk
7530#define HRTIM_SET1R_TIMEVNT4_Pos (15U)
7531#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)
7532#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk
7533#define HRTIM_SET1R_TIMEVNT5_Pos (16U)
7534#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)
7535#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk
7536#define HRTIM_SET1R_TIMEVNT6_Pos (17U)
7537#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)
7538#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk
7539#define HRTIM_SET1R_TIMEVNT7_Pos (18U)
7540#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)
7541#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk
7542#define HRTIM_SET1R_TIMEVNT8_Pos (19U)
7543#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)
7544#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk
7545#define HRTIM_SET1R_TIMEVNT9_Pos (20U)
7546#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)
7547#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk
7549#define HRTIM_SET1R_EXTVNT1_Pos (21U)
7550#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)
7551#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk
7552#define HRTIM_SET1R_EXTVNT2_Pos (22U)
7553#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)
7554#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk
7555#define HRTIM_SET1R_EXTVNT3_Pos (23U)
7556#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)
7557#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk
7558#define HRTIM_SET1R_EXTVNT4_Pos (24U)
7559#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)
7560#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk
7561#define HRTIM_SET1R_EXTVNT5_Pos (25U)
7562#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)
7563#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk
7564#define HRTIM_SET1R_EXTVNT6_Pos (26U)
7565#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)
7566#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk
7567#define HRTIM_SET1R_EXTVNT7_Pos (27U)
7568#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)
7569#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk
7570#define HRTIM_SET1R_EXTVNT8_Pos (28U)
7571#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)
7572#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk
7573#define HRTIM_SET1R_EXTVNT9_Pos (29U)
7574#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)
7575#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk
7576#define HRTIM_SET1R_EXTVNT10_Pos (30U)
7577#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)
7578#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk
7580#define HRTIM_SET1R_UPDATE_Pos (31U)
7581#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos)
7582#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk
7584/**** Bit definition for Slave Output 1 reset register ************************/
7585#define HRTIM_RST1R_SRT_Pos (0U)
7586#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos)
7587#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk
7588#define HRTIM_RST1R_RESYNC_Pos (1U)
7589#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos)
7590#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk
7591#define HRTIM_RST1R_PER_Pos (2U)
7592#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos)
7593#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk
7594#define HRTIM_RST1R_CMP1_Pos (3U)
7595#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos)
7596#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk
7597#define HRTIM_RST1R_CMP2_Pos (4U)
7598#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos)
7599#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk
7600#define HRTIM_RST1R_CMP3_Pos (5U)
7601#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos)
7602#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk
7603#define HRTIM_RST1R_CMP4_Pos (6U)
7604#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos)
7605#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk
7607#define HRTIM_RST1R_MSTPER_Pos (7U)
7608#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos)
7609#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk
7610#define HRTIM_RST1R_MSTCMP1_Pos (8U)
7611#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)
7612#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk
7613#define HRTIM_RST1R_MSTCMP2_Pos (9U)
7614#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)
7615#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk
7616#define HRTIM_RST1R_MSTCMP3_Pos (10U)
7617#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)
7618#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk
7619#define HRTIM_RST1R_MSTCMP4_Pos (11U)
7620#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)
7621#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk
7623#define HRTIM_RST1R_TIMEVNT1_Pos (12U)
7624#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)
7625#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk
7626#define HRTIM_RST1R_TIMEVNT2_Pos (13U)
7627#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)
7628#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk
7629#define HRTIM_RST1R_TIMEVNT3_Pos (14U)
7630#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)
7631#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk
7632#define HRTIM_RST1R_TIMEVNT4_Pos (15U)
7633#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)
7634#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk
7635#define HRTIM_RST1R_TIMEVNT5_Pos (16U)
7636#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)
7637#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk
7638#define HRTIM_RST1R_TIMEVNT6_Pos (17U)
7639#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)
7640#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk
7641#define HRTIM_RST1R_TIMEVNT7_Pos (18U)
7642#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)
7643#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk
7644#define HRTIM_RST1R_TIMEVNT8_Pos (19U)
7645#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)
7646#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk
7647#define HRTIM_RST1R_TIMEVNT9_Pos (20U)
7648#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)
7649#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk
7651#define HRTIM_RST1R_EXTVNT1_Pos (21U)
7652#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)
7653#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk
7654#define HRTIM_RST1R_EXTVNT2_Pos (22U)
7655#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)
7656#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk
7657#define HRTIM_RST1R_EXTVNT3_Pos (23U)
7658#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)
7659#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk
7660#define HRTIM_RST1R_EXTVNT4_Pos (24U)
7661#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)
7662#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk
7663#define HRTIM_RST1R_EXTVNT5_Pos (25U)
7664#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)
7665#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk
7666#define HRTIM_RST1R_EXTVNT6_Pos (26U)
7667#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)
7668#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk
7669#define HRTIM_RST1R_EXTVNT7_Pos (27U)
7670#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)
7671#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk
7672#define HRTIM_RST1R_EXTVNT8_Pos (28U)
7673#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)
7674#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk
7675#define HRTIM_RST1R_EXTVNT9_Pos (29U)
7676#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)
7677#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk
7678#define HRTIM_RST1R_EXTVNT10_Pos (30U)
7679#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)
7680#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk
7681#define HRTIM_RST1R_UPDATE_Pos (31U)
7682#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos)
7683#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk
7685/**** Bit definition for Slave Output 2 set register **************************/
7686#define HRTIM_SET2R_SST_Pos (0U)
7687#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos)
7688#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk
7689#define HRTIM_SET2R_RESYNC_Pos (1U)
7690#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos)
7691#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk
7692#define HRTIM_SET2R_PER_Pos (2U)
7693#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos)
7694#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk
7695#define HRTIM_SET2R_CMP1_Pos (3U)
7696#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos)
7697#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk
7698#define HRTIM_SET2R_CMP2_Pos (4U)
7699#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos)
7700#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk
7701#define HRTIM_SET2R_CMP3_Pos (5U)
7702#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos)
7703#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk
7704#define HRTIM_SET2R_CMP4_Pos (6U)
7705#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos)
7706#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk
7708#define HRTIM_SET2R_MSTPER_Pos (7U)
7709#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos)
7710#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk
7711#define HRTIM_SET2R_MSTCMP1_Pos (8U)
7712#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)
7713#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk
7714#define HRTIM_SET2R_MSTCMP2_Pos (9U)
7715#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)
7716#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk
7717#define HRTIM_SET2R_MSTCMP3_Pos (10U)
7718#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)
7719#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk
7720#define HRTIM_SET2R_MSTCMP4_Pos (11U)
7721#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)
7722#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk
7724#define HRTIM_SET2R_TIMEVNT1_Pos (12U)
7725#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)
7726#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk
7727#define HRTIM_SET2R_TIMEVNT2_Pos (13U)
7728#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)
7729#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk
7730#define HRTIM_SET2R_TIMEVNT3_Pos (14U)
7731#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)
7732#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk
7733#define HRTIM_SET2R_TIMEVNT4_Pos (15U)
7734#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)
7735#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk
7736#define HRTIM_SET2R_TIMEVNT5_Pos (16U)
7737#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)
7738#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk
7739#define HRTIM_SET2R_TIMEVNT6_Pos (17U)
7740#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)
7741#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk
7742#define HRTIM_SET2R_TIMEVNT7_Pos (18U)
7743#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)
7744#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk
7745#define HRTIM_SET2R_TIMEVNT8_Pos (19U)
7746#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)
7747#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk
7748#define HRTIM_SET2R_TIMEVNT9_Pos (20U)
7749#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)
7750#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk
7752#define HRTIM_SET2R_EXTVNT1_Pos (21U)
7753#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)
7754#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk
7755#define HRTIM_SET2R_EXTVNT2_Pos (22U)
7756#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)
7757#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk
7758#define HRTIM_SET2R_EXTVNT3_Pos (23U)
7759#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)
7760#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk
7761#define HRTIM_SET2R_EXTVNT4_Pos (24U)
7762#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)
7763#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk
7764#define HRTIM_SET2R_EXTVNT5_Pos (25U)
7765#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)
7766#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk
7767#define HRTIM_SET2R_EXTVNT6_Pos (26U)
7768#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)
7769#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk
7770#define HRTIM_SET2R_EXTVNT7_Pos (27U)
7771#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)
7772#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk
7773#define HRTIM_SET2R_EXTVNT8_Pos (28U)
7774#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)
7775#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk
7776#define HRTIM_SET2R_EXTVNT9_Pos (29U)
7777#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)
7778#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk
7779#define HRTIM_SET2R_EXTVNT10_Pos (30U)
7780#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)
7781#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk
7783#define HRTIM_SET2R_UPDATE_Pos (31U)
7784#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos)
7785#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk
7787/**** Bit definition for Slave Output 2 reset register ************************/
7788#define HRTIM_RST2R_SRT_Pos (0U)
7789#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos)
7790#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk
7791#define HRTIM_RST2R_RESYNC_Pos (1U)
7792#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos)
7793#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk
7794#define HRTIM_RST2R_PER_Pos (2U)
7795#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos)
7796#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk
7797#define HRTIM_RST2R_CMP1_Pos (3U)
7798#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos)
7799#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk
7800#define HRTIM_RST2R_CMP2_Pos (4U)
7801#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos)
7802#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk
7803#define HRTIM_RST2R_CMP3_Pos (5U)
7804#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos)
7805#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk
7806#define HRTIM_RST2R_CMP4_Pos (6U)
7807#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos)
7808#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk
7809#define HRTIM_RST2R_MSTPER_Pos (7U)
7810#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos)
7811#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk
7812#define HRTIM_RST2R_MSTCMP1_Pos (8U)
7813#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)
7814#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk
7815#define HRTIM_RST2R_MSTCMP2_Pos (9U)
7816#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)
7817#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk
7818#define HRTIM_RST2R_MSTCMP3_Pos (10U)
7819#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)
7820#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk
7821#define HRTIM_RST2R_MSTCMP4_Pos (11U)
7822#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)
7823#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk
7825#define HRTIM_RST2R_TIMEVNT1_Pos (12U)
7826#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)
7827#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk
7828#define HRTIM_RST2R_TIMEVNT2_Pos (13U)
7829#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)
7830#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk
7831#define HRTIM_RST2R_TIMEVNT3_Pos (14U)
7832#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)
7833#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk
7834#define HRTIM_RST2R_TIMEVNT4_Pos (15U)
7835#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)
7836#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk
7837#define HRTIM_RST2R_TIMEVNT5_Pos (16U)
7838#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)
7839#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk
7840#define HRTIM_RST2R_TIMEVNT6_Pos (17U)
7841#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)
7842#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk
7843#define HRTIM_RST2R_TIMEVNT7_Pos (18U)
7844#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)
7845#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk
7846#define HRTIM_RST2R_TIMEVNT8_Pos (19U)
7847#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)
7848#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk
7849#define HRTIM_RST2R_TIMEVNT9_Pos (20U)
7850#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)
7851#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk
7853#define HRTIM_RST2R_EXTVNT1_Pos (21U)
7854#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)
7855#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk
7856#define HRTIM_RST2R_EXTVNT2_Pos (22U)
7857#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)
7858#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk
7859#define HRTIM_RST2R_EXTVNT3_Pos (23U)
7860#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)
7861#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk
7862#define HRTIM_RST2R_EXTVNT4_Pos (24U)
7863#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)
7864#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk
7865#define HRTIM_RST2R_EXTVNT5_Pos (25U)
7866#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)
7867#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk
7868#define HRTIM_RST2R_EXTVNT6_Pos (26U)
7869#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)
7870#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk
7871#define HRTIM_RST2R_EXTVNT7_Pos (27U)
7872#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)
7873#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk
7874#define HRTIM_RST2R_EXTVNT8_Pos (28U)
7875#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)
7876#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk
7877#define HRTIM_RST2R_EXTVNT9_Pos (29U)
7878#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)
7879#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk
7880#define HRTIM_RST2R_EXTVNT10_Pos (30U)
7881#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)
7882#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk
7883#define HRTIM_RST2R_UPDATE_Pos (31U)
7884#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos)
7885#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk
7887/**** Bit definition for Slave external event filtering register 1 ***********/
7888#define HRTIM_EEFR1_EE1LTCH_Pos (0U)
7889#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)
7890#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk
7891#define HRTIM_EEFR1_EE1FLTR_Pos (1U)
7892#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)
7893#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk
7894#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)
7895#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)
7896#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)
7897#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)
7899#define HRTIM_EEFR1_EE2LTCH_Pos (6U)
7900#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)
7901#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk
7902#define HRTIM_EEFR1_EE2FLTR_Pos (7U)
7903#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)
7904#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk
7905#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)
7906#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)
7907#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)
7908#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)
7910#define HRTIM_EEFR1_EE3LTCH_Pos (12U)
7911#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)
7912#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk
7913#define HRTIM_EEFR1_EE3FLTR_Pos (13U)
7914#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)
7915#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk
7916#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)
7917#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)
7918#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)
7919#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)
7921#define HRTIM_EEFR1_EE4LTCH_Pos (18U)
7922#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)
7923#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk
7924#define HRTIM_EEFR1_EE4FLTR_Pos (19U)
7925#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)
7926#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk
7927#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)
7928#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)
7929#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)
7930#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)
7932#define HRTIM_EEFR1_EE5LTCH_Pos (24U)
7933#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)
7934#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk
7935#define HRTIM_EEFR1_EE5FLTR_Pos (25U)
7936#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)
7937#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk
7938#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)
7939#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)
7940#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)
7941#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)
7943/**** Bit definition for Slave external event filtering register 2 ***********/
7944#define HRTIM_EEFR2_EE6LTCH_Pos (0U)
7945#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)
7946#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk
7947#define HRTIM_EEFR2_EE6FLTR_Pos (1U)
7948#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)
7949#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk
7950#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)
7951#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)
7952#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)
7953#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)
7955#define HRTIM_EEFR2_EE7LTCH_Pos (6U)
7956#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)
7957#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk
7958#define HRTIM_EEFR2_EE7FLTR_Pos (7U)
7959#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)
7960#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk
7961#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)
7962#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)
7963#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)
7964#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)
7966#define HRTIM_EEFR2_EE8LTCH_Pos (12U)
7967#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)
7968#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk
7969#define HRTIM_EEFR2_EE8FLTR_Pos (13U)
7970#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)
7971#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk
7972#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)
7973#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)
7974#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)
7975#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)
7977#define HRTIM_EEFR2_EE9LTCH_Pos (18U)
7978#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)
7979#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk
7980#define HRTIM_EEFR2_EE9FLTR_Pos (19U)
7981#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)
7982#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk
7983#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)
7984#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)
7985#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)
7986#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)
7988#define HRTIM_EEFR2_EE10LTCH_Pos (24U)
7989#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)
7990#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk
7991#define HRTIM_EEFR2_EE10FLTR_Pos (25U)
7992#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)
7993#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk
7994#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)
7995#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)
7996#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)
7997#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)
7999/**** Bit definition for Slave Timer reset register ***************************/
8000
8001#define HRTIM_RSTR_TIMFCMP1_Pos (0U)
8002#define HRTIM_RSTR_TIMFCMP1_Msk (0x1UL << HRTIM_RSTR_TIMFCMP1_Pos)
8003#define HRTIM_RSTR_TIMFCMP1 HRTIM_RSTR_TIMFCMP1_Msk
8004#define HRTIM_RSTR_UPDATE_Pos (1U)
8005#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos)
8006#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk
8007#define HRTIM_RSTR_CMP2_Pos (2U)
8008#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos)
8009#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk
8010#define HRTIM_RSTR_CMP4_Pos (3U)
8011#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos)
8012#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk
8013#define HRTIM_RSTR_MSTPER_Pos (4U)
8014#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos)
8015#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk
8016#define HRTIM_RSTR_MSTCMP1_Pos (5U)
8017#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)
8018#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk
8019#define HRTIM_RSTR_MSTCMP2_Pos (6U)
8020#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)
8021#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk
8022#define HRTIM_RSTR_MSTCMP3_Pos (7U)
8023#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)
8024#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk
8025#define HRTIM_RSTR_MSTCMP4_Pos (8U)
8026#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)
8027#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk
8028#define HRTIM_RSTR_EXTEVNT1_Pos (9U)
8029#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)
8030#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk
8031#define HRTIM_RSTR_EXTEVNT2_Pos (10U)
8032#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)
8033#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk
8034#define HRTIM_RSTR_EXTEVNT3_Pos (11U)
8035#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)
8036#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk
8037#define HRTIM_RSTR_EXTEVNT4_Pos (12U)
8038#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)
8039#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk
8040#define HRTIM_RSTR_EXTEVNT5_Pos (13U)
8041#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)
8042#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk
8043#define HRTIM_RSTR_EXTEVNT6_Pos (14U)
8044#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)
8045#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk
8046#define HRTIM_RSTR_EXTEVNT7_Pos (15U)
8047#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)
8048#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk
8049#define HRTIM_RSTR_EXTEVNT8_Pos (16U)
8050#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)
8051#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk
8052#define HRTIM_RSTR_EXTEVNT9_Pos (17U)
8053#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)
8054#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk
8055#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
8056#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)
8057#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk
8059/* Slave Timer A reset enable bits upon other slave timers events */
8060#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
8061#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)
8062#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk
8063#define HRTIM_RSTR_TIMBCMP2_Pos (20U)
8064#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)
8065#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk
8066#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
8067#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)
8068#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk
8070#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
8071#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)
8072#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk
8073#define HRTIM_RSTR_TIMCCMP2_Pos (23U)
8074#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)
8075#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk
8076#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
8077#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)
8078#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk
8080#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
8081#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)
8082#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk
8083#define HRTIM_RSTR_TIMDCMP2_Pos (26U)
8084#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)
8085#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk
8086#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
8087#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)
8088#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk
8090#define HRTIM_RSTR_TIMECMP1_Pos (28U)
8091#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)
8092#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk
8093#define HRTIM_RSTR_TIMECMP2_Pos (29U)
8094#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)
8095#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk
8096#define HRTIM_RSTR_TIMECMP4_Pos (30U)
8097#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)
8098#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk
8100#define HRTIM_RSTR_TIMFCMP2_Pos (31U)
8101#define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos)
8102#define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk
8104/* Slave Timer B reset enable bits upon other slave timers events */
8105#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
8106#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)
8107#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk
8108#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
8109#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)
8110#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk
8111#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
8112#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)
8113#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk
8115#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
8116#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)
8117#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk
8118#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
8119#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)
8120#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk
8121#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
8122#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)
8123#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk
8125#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
8126#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)
8127#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk
8128#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
8129#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)
8130#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk
8131#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
8132#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)
8133#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk
8135#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
8136#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)
8137#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk
8138#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
8139#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)
8140#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk
8141#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
8142#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)
8143#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk
8145#define HRTIM_RSTBR_TIMFCMP2_Pos (31U)
8146#define HRTIM_RSTBR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMFCMP2_Pos)
8147#define HRTIM_RSTBR_TIMFCMP2 HRTIM_RSTBR_TIMFCMP2_Msk
8149/* Slave Timer C reset enable bits upon other slave timers events */
8150#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
8151#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)
8152#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk
8153#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
8154#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)
8155#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk
8156#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
8157#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)
8158#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk
8160#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
8161#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)
8162#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk
8163#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
8164#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)
8165#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk
8166#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
8167#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)
8168#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk
8170#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
8171#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)
8172#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk
8173#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
8174#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)
8175#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk
8176#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
8177#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)
8178#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk
8180#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
8181#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)
8182#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk
8183#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
8184#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)
8185#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk
8186#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
8187#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)
8188#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk
8190#define HRTIM_RSTCR_TIMFCMP2_Pos (31U)
8191#define HRTIM_RSTCR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMFCMP2_Pos)
8192#define HRTIM_RSTCR_TIMFCMP2 HRTIM_RSTCR_TIMFCMP2_Msk
8194/* Slave Timer D reset enable bits upon other slave timers events */
8195#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
8196#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)
8197#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk
8198#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
8199#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)
8200#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk
8201#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
8202#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)
8203#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk
8205#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
8206#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)
8207#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk
8208#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
8209#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)
8210#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk
8211#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
8212#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)
8213#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk
8215#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
8216#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)
8217#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk
8218#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
8219#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)
8220#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk
8221#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
8222#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)
8223#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk
8225#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
8226#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)
8227#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk
8228#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
8229#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)
8230#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk
8231#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
8232#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)
8233#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk
8235#define HRTIM_RSTDR_TIMFCMP2_Pos (31U)
8236#define HRTIM_RSTDR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMFCMP2_Pos)
8237#define HRTIM_RSTDR_TIMFCMP2 HRTIM_RSTDR_TIMFCMP2_Msk
8239/* Slave Timer E reset enable bits upon other slave timers events */
8240#define HRTIM_RSTER_TIMACMP1_Pos (19U)
8241#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)
8242#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk
8243#define HRTIM_RSTER_TIMACMP2_Pos (20U)
8244#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)
8245#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk
8246#define HRTIM_RSTER_TIMACMP4_Pos (21U)
8247#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)
8248#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk
8250#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
8251#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)
8252#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk
8253#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
8254#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)
8255#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk
8256#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
8257#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)
8258#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk
8260#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
8261#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)
8262#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk
8263#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
8264#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)
8265#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk
8266#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
8267#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)
8268#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk
8270#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
8271#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)
8272#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk
8273#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
8274#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)
8275#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk
8276#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
8277#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)
8278#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk
8280#define HRTIM_RSTER_TIMFCMP2_Pos (31U)
8281#define HRTIM_RSTER_TIMFCMP2_Msk (0x1UL << HRTIM_RSTER_TIMFCMP2_Pos)
8282#define HRTIM_RSTER_TIMFCMP2 HRTIM_RSTER_TIMFCMP2_Msk
8284/* Slave Timer F reset enable bits upon other slave timers events */
8285#define HRTIM_RSTFR_TIMACMP1_Pos (19U)
8286#define HRTIM_RSTFR_TIMACMP1_Msk (0x1UL << HRTIM_RSTFR_TIMACMP1_Pos)
8287#define HRTIM_RSTFR_TIMACMP1 HRTIM_RSTFR_TIMACMP1_Msk
8288#define HRTIM_RSTFR_TIMACMP2_Pos (20U)
8289#define HRTIM_RSTFR_TIMACMP2_Msk (0x1UL << HRTIM_RSTFR_TIMACMP2_Pos)
8290#define HRTIM_RSTFR_TIMACMP2 HRTIM_RSTFR_TIMACMP2_Msk
8291#define HRTIM_RSTFR_TIMACMP4_Pos (21U)
8292#define HRTIM_RSTFR_TIMACMP4_Msk (0x1UL << HRTIM_RSTFR_TIMACMP4_Pos)
8293#define HRTIM_RSTFR_TIMACMP4 HRTIM_RSTFR_TIMACMP4_Msk
8295#define HRTIM_RSTFR_TIMBCMP1_Pos (22U)
8296#define HRTIM_RSTFR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP1_Pos)
8297#define HRTIM_RSTFR_TIMBCMP1 HRTIM_RSTFR_TIMBCMP1_Msk
8298#define HRTIM_RSTFR_TIMBCMP2_Pos (23U)
8299#define HRTIM_RSTFR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP2_Pos)
8300#define HRTIM_RSTFR_TIMBCMP2 HRTIM_RSTFR_TIMBCMP2_Msk
8301#define HRTIM_RSTFR_TIMBCMP4_Pos (24U)
8302#define HRTIM_RSTFR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP4_Pos)
8303#define HRTIM_RSTFR_TIMBCMP4 HRTIM_RSTFR_TIMBCMP4_Msk
8305#define HRTIM_RSTFR_TIMCCMP1_Pos (25U)
8306#define HRTIM_RSTFR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP1_Pos)
8307#define HRTIM_RSTFR_TIMCCMP1 HRTIM_RSTFR_TIMCCMP1_Msk
8308#define HRTIM_RSTFR_TIMCCMP2_Pos (26U)
8309#define HRTIM_RSTFR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP2_Pos)
8310#define HRTIM_RSTFR_TIMCCMP2 HRTIM_RSTFR_TIMCCMP2_Msk
8311#define HRTIM_RSTFR_TIMCCMP4_Pos (27U)
8312#define HRTIM_RSTFR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP4_Pos)
8313#define HRTIM_RSTFR_TIMCCMP4 HRTIM_RSTFR_TIMCCMP4_Msk
8315#define HRTIM_RSTFR_TIMDCMP1_Pos (28U)
8316#define HRTIM_RSTFR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP1_Pos)
8317#define HRTIM_RSTFR_TIMDCMP1 HRTIM_RSTFR_TIMDCMP1_Msk
8318#define HRTIM_RSTFR_TIMDCMP2_Pos (29U)
8319#define HRTIM_RSTFR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP2_Pos)
8320#define HRTIM_RSTFR_TIMDCMP2 HRTIM_RSTFR_TIMDCMP2_Msk
8321#define HRTIM_RSTFR_TIMDCMP4_Pos (30U)
8322#define HRTIM_RSTFR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP4_Pos)
8323#define HRTIM_RSTFR_TIMDCMP4 HRTIM_RSTFR_TIMDCMP4_Msk
8325#define HRTIM_RSTFR_TIMECMP2_Pos (31U)
8326#define HRTIM_RSTFR_TIMECMP2_Msk (0x1UL << HRTIM_RSTFR_TIMECMP2_Pos)
8327#define HRTIM_RSTFR_TIMECMP2 HRTIM_RSTFR_TIMECMP2_Msk
8329/**** Bit definition for Slave Timer Chopper register *************************/
8330#define HRTIM_CHPR_CARFRQ_Pos (0U)
8331#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos)
8332#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk
8333#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos)
8334#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos)
8335#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos)
8336#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos)
8338#define HRTIM_CHPR_CARDTY_Pos (4U)
8339#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos)
8340#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk
8341#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos)
8342#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos)
8343#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos)
8345#define HRTIM_CHPR_STRPW_Pos (7U)
8346#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos)
8347#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk
8348#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos)
8349#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos)
8350#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos)
8351#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos)
8353/**** Bit definition for Slave Timer Capture 1 control register ***************/
8354#define HRTIM_CPT1CR_SWCPT_Pos (0U)
8355#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)
8356#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk
8357#define HRTIM_CPT1CR_UPDCPT_Pos (1U)
8358#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)
8359#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk
8360#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
8361#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)
8362#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk
8363#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
8364#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)
8365#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk
8366#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
8367#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)
8368#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk
8369#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
8370#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)
8371#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk
8372#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
8373#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)
8374#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk
8375#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
8376#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)
8377#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk
8378#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
8379#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)
8380#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk
8381#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
8382#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)
8383#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk
8384#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
8385#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)
8386#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk
8387#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
8388#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)
8389#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk
8391#define HRTIM_CPT1CR_TF1SET_Pos (0U)
8392#define HRTIM_CPT1CR_TF1SET_Msk (0x1UL << HRTIM_CPT1CR_TF1SET_Pos)
8393#define HRTIM_CPT1CR_TF1SET HRTIM_CPT1CR_TF1SET_Msk
8394#define HRTIM_CPT1CR_TF1RST_Pos (1U)
8395#define HRTIM_CPT1CR_TF1RST_Msk (0x1UL << HRTIM_CPT1CR_TF1RST_Pos)
8396#define HRTIM_CPT1CR_TF1RST HRTIM_CPT1CR_TF1RST_Msk
8397#define HRTIM_CPT1CR_TIMFCMP1_Pos (2U)
8398#define HRTIM_CPT1CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP1_Pos)
8399#define HRTIM_CPT1CR_TIMFCMP1 HRTIM_CPT1CR_TIMFCMP1_Msk
8400#define HRTIM_CPT1CR_TIMFCMP2_Pos (3U)
8401#define HRTIM_CPT1CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP2_Pos)
8402#define HRTIM_CPT1CR_TIMFCMP2 HRTIM_CPT1CR_TIMFCMP2_Msk
8404#define HRTIM_CPT1CR_TA1SET_Pos (12U)
8405#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)
8406#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk
8407#define HRTIM_CPT1CR_TA1RST_Pos (13U)
8408#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)
8409#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk
8410#define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
8411#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)
8412#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk
8413#define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
8414#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)
8415#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk
8417#define HRTIM_CPT1CR_TB1SET_Pos (16U)
8418#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)
8419#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk
8420#define HRTIM_CPT1CR_TB1RST_Pos (17U)
8421#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)
8422#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk
8423#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
8424#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)
8425#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk
8426#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
8427#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)
8428#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk
8430#define HRTIM_CPT1CR_TC1SET_Pos (20U)
8431#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)
8432#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk
8433#define HRTIM_CPT1CR_TC1RST_Pos (21U)
8434#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)
8435#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk
8436#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
8437#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)
8438#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk
8439#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
8440#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)
8441#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk
8443#define HRTIM_CPT1CR_TD1SET_Pos (24U)
8444#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)
8445#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk
8446#define HRTIM_CPT1CR_TD1RST_Pos (25U)
8447#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)
8448#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk
8449#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
8450#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)
8451#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk
8452#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
8453#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)
8454#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk
8456#define HRTIM_CPT1CR_TE1SET_Pos (28U)
8457#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)
8458#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk
8459#define HRTIM_CPT1CR_TE1RST_Pos (29U)
8460#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)
8461#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk
8462#define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
8463#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)
8464#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk
8465#define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
8466#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)
8467#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk
8469/**** Bit definition for Slave Timer Capture 2 control register ***************/
8470#define HRTIM_CPT2CR_SWCPT_Pos (0U)
8471#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)
8472#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk
8473#define HRTIM_CPT2CR_UPDCPT_Pos (1U)
8474#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)
8475#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk
8476#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
8477#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)
8478#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk
8479#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
8480#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)
8481#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk
8482#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
8483#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)
8484#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk
8485#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
8486#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)
8487#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk
8488#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
8489#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)
8490#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk
8491#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
8492#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)
8493#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk
8494#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
8495#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)
8496#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk
8497#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
8498#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)
8499#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk
8500#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
8501#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)
8502#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk
8503#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
8504#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)
8505#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk
8507#define HRTIM_CPT2CR_TF1SET_Pos (0U)
8508#define HRTIM_CPT2CR_TF1SET_Msk (0x1UL << HRTIM_CPT2CR_TF1SET_Pos)
8509#define HRTIM_CPT2CR_TF1SET HRTIM_CPT2CR_TF1SET_Msk
8510#define HRTIM_CPT2CR_TF1RST_Pos (1U)
8511#define HRTIM_CPT2CR_TF1RST_Msk (0x1UL << HRTIM_CPT2CR_TF1RST_Pos)
8512#define HRTIM_CPT2CR_TF1RST HRTIM_CPT2CR_TF1RST_Msk
8513#define HRTIM_CPT2CR_TIMFCMP1_Pos (2U)
8514#define HRTIM_CPT2CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP1_Pos)
8515#define HRTIM_CPT2CR_TIMFCMP1 HRTIM_CPT2CR_TIMFCMP1_Msk
8516#define HRTIM_CPT2CR_TIMFCMP2_Pos (3U)
8517#define HRTIM_CPT2CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP2_Pos)
8518#define HRTIM_CPT2CR_TIMFCMP2 HRTIM_CPT2CR_TIMFCMP2_Msk
8520#define HRTIM_CPT2CR_TA1SET_Pos (12U)
8521#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)
8522#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk
8523#define HRTIM_CPT2CR_TA1RST_Pos (13U)
8524#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)
8525#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk
8526#define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
8527#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)
8528#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk
8529#define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
8530#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)
8531#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk
8533#define HRTIM_CPT2CR_TB1SET_Pos (16U)
8534#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)
8535#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk
8536#define HRTIM_CPT2CR_TB1RST_Pos (17U)
8537#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)
8538#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk
8539#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
8540#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)
8541#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk
8542#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
8543#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)
8544#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk
8546#define HRTIM_CPT2CR_TC1SET_Pos (20U)
8547#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)
8548#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk
8549#define HRTIM_CPT2CR_TC1RST_Pos (21U)
8550#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)
8551#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk
8552#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
8553#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)
8554#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk
8555#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
8556#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)
8557#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk
8559#define HRTIM_CPT2CR_TD1SET_Pos (24U)
8560#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)
8561#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk
8562#define HRTIM_CPT2CR_TD1RST_Pos (25U)
8563#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)
8564#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk
8565#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
8566#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)
8567#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk
8568#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
8569#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)
8570#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk
8572#define HRTIM_CPT2CR_TE1SET_Pos (28U)
8573#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)
8574#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk
8575#define HRTIM_CPT2CR_TE1RST_Pos (29U)
8576#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)
8577#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk
8578#define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
8579#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)
8580#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk
8581#define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
8582#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)
8583#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk
8585/**** Bit definition for Slave Timer Output register **************************/
8586#define HRTIM_OUTR_POL1_Pos (1U)
8587#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos)
8588#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk
8589#define HRTIM_OUTR_IDLM1_Pos (2U)
8590#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos)
8591#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk
8592#define HRTIM_OUTR_IDLES1_Pos (3U)
8593#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos)
8594#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk
8595#define HRTIM_OUTR_FAULT1_Pos (4U)
8596#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos)
8597#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk
8598#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos)
8599#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos)
8600#define HRTIM_OUTR_CHP1_Pos (6U)
8601#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos)
8602#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk
8603#define HRTIM_OUTR_DIDL1_Pos (7U)
8604#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos)
8605#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk
8607#define HRTIM_OUTR_DTEN_Pos (8U)
8608#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos)
8609#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk
8610#define HRTIM_OUTR_DLYPRTEN_Pos (9U)
8611#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)
8612#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk
8613#define HRTIM_OUTR_DLYPRT_Pos (10U)
8614#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos)
8615#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk
8616#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos)
8617#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos)
8618#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos)
8619#define HRTIM_OUTR_BIAR_Pos (14U)
8620#define HRTIM_OUTR_BIAR_Msk (0x1UL << HRTIM_OUTR_BIAR_Pos)
8621#define HRTIM_OUTR_BIAR HRTIM_OUTR_BIAR_Msk
8622#define HRTIM_OUTR_POL2_Pos (17U)
8623#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos)
8624#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk
8625#define HRTIM_OUTR_IDLM2_Pos (18U)
8626#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos)
8627#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk
8628#define HRTIM_OUTR_IDLES2_Pos (19U)
8629#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos)
8630#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk
8631#define HRTIM_OUTR_FAULT2_Pos (20U)
8632#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos)
8633#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk
8634#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos)
8635#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos)
8636#define HRTIM_OUTR_CHP2_Pos (22U)
8637#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos)
8638#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk
8639#define HRTIM_OUTR_DIDL2_Pos (23U)
8640#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos)
8641#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk
8643/**** Bit definition for Timerx Fault register ***************************/
8644#define HRTIM_FLTR_FLT1EN_Pos (0U)
8645#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos)
8646#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk
8647#define HRTIM_FLTR_FLT2EN_Pos (1U)
8648#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos)
8649#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk
8650#define HRTIM_FLTR_FLT3EN_Pos (2U)
8651#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos)
8652#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk
8653#define HRTIM_FLTR_FLT4EN_Pos (3U)
8654#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos)
8655#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk
8656#define HRTIM_FLTR_FLT5EN_Pos (4U)
8657#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos)
8658#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk
8659#define HRTIM_FLTR_FLT6EN_Pos (5U)
8660#define HRTIM_FLTR_FLT6EN_Msk (0x1UL << HRTIM_FLTR_FLT6EN_Pos)
8661#define HRTIM_FLTR_FLT6EN HRTIM_FLTR_FLT6EN_Msk
8662#define HRTIM_FLTR_FLTLCK_Pos (31U)
8663#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos)
8664#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk
8666/**** Bit definition for HRTIM Timerx control register 2 ****************/
8667#define HRTIM_TIMCR2_DCDE_Pos (0U)
8668#define HRTIM_TIMCR2_DCDE_Msk (0x1UL << HRTIM_TIMCR2_DCDE_Pos)
8669#define HRTIM_TIMCR2_DCDE HRTIM_TIMCR2_DCDE_Msk
8670#define HRTIM_TIMCR2_DCDS_Pos (1U)
8671#define HRTIM_TIMCR2_DCDS_Msk (0x1UL << HRTIM_TIMCR2_DCDS_Pos)
8672#define HRTIM_TIMCR2_DCDS HRTIM_TIMCR2_DCDS_Msk
8673#define HRTIM_TIMCR2_DCDR_Pos (2U)
8674#define HRTIM_TIMCR2_DCDR_Msk (0x1UL << HRTIM_TIMCR2_DCDR_Pos)
8675#define HRTIM_TIMCR2_DCDR HRTIM_TIMCR2_DCDR_Msk
8676#define HRTIM_TIMCR2_UDM_Pos (4U)
8677#define HRTIM_TIMCR2_UDM_Msk (0x1UL << HRTIM_TIMCR2_UDM_Pos)
8678#define HRTIM_TIMCR2_UDM HRTIM_TIMCR2_UDM_Msk
8679#define HRTIM_TIMCR2_ROM_Pos (6U)
8680#define HRTIM_TIMCR2_ROM_Msk (0x3UL << HRTIM_TIMCR2_ROM_Pos)
8681#define HRTIM_TIMCR2_ROM HRTIM_TIMCR2_ROM_Msk
8682#define HRTIM_TIMCR2_ROM_0 (0x1UL << HRTIM_TIMCR2_ROM_Pos)
8683#define HRTIM_TIMCR2_ROM_1 (0x2UL << HRTIM_TIMCR2_ROM_Pos)
8684#define HRTIM_TIMCR2_OUTROM_Pos (8U)
8685#define HRTIM_TIMCR2_OUTROM_Msk (0x3UL << HRTIM_TIMCR2_OUTROM_Pos)
8686#define HRTIM_TIMCR2_OUTROM HRTIM_TIMCR2_OUTROM_Msk
8687#define HRTIM_TIMCR2_OUTROM_0 (0x1UL << HRTIM_TIMCR2_OUTROM_Pos)
8688#define HRTIM_TIMCR2_OUTROM_1 (0x2UL << HRTIM_TIMCR2_OUTROM_Pos)
8689#define HRTIM_TIMCR2_ADROM_Pos (10U)
8690#define HRTIM_TIMCR2_ADROM_Msk (0x3UL << HRTIM_TIMCR2_ADROM_Pos)
8691#define HRTIM_TIMCR2_ADROM HRTIM_TIMCR2_ADROM_Msk
8692#define HRTIM_TIMCR2_ADROM_0 (0x1UL << HRTIM_TIMCR2_ADROM_Pos)
8693#define HRTIM_TIMCR2_ADROM_1 (0x2UL << HRTIM_TIMCR2_ADROM_Pos)
8694#define HRTIM_TIMCR2_BMROM_Pos (12U)
8695#define HRTIM_TIMCR2_BMROM_Msk (0x3UL << HRTIM_TIMCR2_BMROM_Pos)
8696#define HRTIM_TIMCR2_BMROM HRTIM_TIMCR2_BMROM_Msk
8697#define HRTIM_TIMCR2_BMROM_0 (0x1UL << HRTIM_TIMCR2_BMROM_Pos)
8698#define HRTIM_TIMCR2_BMROM_1 (0x2UL << HRTIM_TIMCR2_BMROM_Pos)
8699#define HRTIM_TIMCR2_FEROM_Pos (14U)
8700#define HRTIM_TIMCR2_FEROM_Msk (0x3UL << HRTIM_TIMCR2_FEROM_Pos)
8701#define HRTIM_TIMCR2_FEROM HRTIM_TIMCR2_FEROM_Msk
8702#define HRTIM_TIMCR2_FEROM_0 (0x1UL << HRTIM_TIMCR2_FEROM_Pos)
8703#define HRTIM_TIMCR2_FEROM_1 (0x2UL << HRTIM_TIMCR2_FEROM_Pos)
8704#define HRTIM_TIMCR2_GTCMP1_Pos (16U)
8705#define HRTIM_TIMCR2_GTCMP1_Msk (0x1UL << HRTIM_TIMCR2_GTCMP1_Pos)
8706#define HRTIM_TIMCR2_GTCMP1 HRTIM_TIMCR2_GTCMP1_Msk
8707#define HRTIM_TIMCR2_GTCMP3_Pos (17U)
8708#define HRTIM_TIMCR2_GTCMP3_Msk (0x1UL << HRTIM_TIMCR2_GTCMP3_Pos)
8709#define HRTIM_TIMCR2_GTCMP3 HRTIM_TIMCR2_GTCMP3_Msk
8710#define HRTIM_TIMCR2_TRGHLF_Pos (20U)
8711#define HRTIM_TIMCR2_TRGHLF_Msk (0x1UL << HRTIM_TIMCR2_TRGHLF_Pos)
8712#define HRTIM_TIMCR2_TRGHLF HRTIM_TIMCR2_TRGHLF_Msk
8714/**** Bit definition for Slave external event filtering register 3 ***********/
8715#define HRTIM_EEFR3_EEVACE_Pos (0U)
8716#define HRTIM_EEFR3_EEVACE_Msk (0x1UL << HRTIM_EEFR3_EEVACE_Pos)
8717#define HRTIM_EEFR3_EEVACE HRTIM_EEFR3_EEVACE_Msk
8718#define HRTIM_EEFR3_EEVACRES_Pos (1U)
8719#define HRTIM_EEFR3_EEVACRES_Msk (0x1UL << HRTIM_EEFR3_EEVACRES_Pos)
8720#define HRTIM_EEFR3_EEVACRES HRTIM_EEFR3_EEVACRES_Msk
8721#define HRTIM_EEFR3_EEVARSTM_Pos (2U)
8722#define HRTIM_EEFR3_EEVARSTM_Msk (0x1UL << HRTIM_EEFR3_EEVARSTM_Pos)
8723#define HRTIM_EEFR3_EEVARSTM HRTIM_EEFR3_EEVARSTM_Msk
8724#define HRTIM_EEFR3_EEVASEL_Pos (4U)
8725#define HRTIM_EEFR3_EEVASEL_Msk (0xFUL << HRTIM_EEFR3_EEVASEL_Pos)
8726#define HRTIM_EEFR3_EEVASEL HRTIM_EEFR3_EEVASEL_Msk
8727#define HRTIM_EEFR3_EEVASEL_0 (0x1UL << HRTIM_EEFR3_EEVASEL_Pos)
8728#define HRTIM_EEFR3_EEVASEL_1 (0x2UL << HRTIM_EEFR3_EEVASEL_Pos)
8729#define HRTIM_EEFR3_EEVASEL_2 (0x4UL << HRTIM_EEFR3_EEVASEL_Pos)
8730#define HRTIM_EEFR3_EEVASEL_3 (0x8UL << HRTIM_EEFR3_EEVASEL_Pos)
8731#define HRTIM_EEFR3_EEVACNT_Pos (8U)
8732#define HRTIM_EEFR3_EEVACNT_Msk (0x3FUL << HRTIM_EEFR3_EEVACNT_Pos)
8733#define HRTIM_EEFR3_EEVACNT HRTIM_EEFR3_EEVACNT_Msk
8734#define HRTIM_EEFR3_EEVACNT_0 (0x1UL << HRTIM_EEFR3_EEVACNT_Pos)
8735#define HRTIM_EEFR3_EEVACNT_1 (0x2UL << HRTIM_EEFR3_EEVACNT_Pos)
8736#define HRTIM_EEFR3_EEVACNT_2 (0x4UL << HRTIM_EEFR3_EEVACNT_Pos)
8737#define HRTIM_EEFR3_EEVACNT_3 (0x8UL << HRTIM_EEFR3_EEVACNT_Pos)
8738#define HRTIM_EEFR3_EEVACNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos)
8739#define HRTIM_EEFR3_EEVACNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos)
8740#define HRTIM_EEFR3_EEVBCE_Pos (16U)
8741#define HRTIM_EEFR3_EEVBCE_Msk (0x1UL << HRTIM_EEFR3_EEVBCE_Pos)
8742#define HRTIM_EEFR3_EEVBCE HRTIM_EEFR3_EEVBCE_Msk
8743#define HRTIM_EEFR3_EEVBCRES_Pos (17U)
8744#define HRTIM_EEFR3_EEVBCRES_Msk (0x1UL << HRTIM_EEFR3_EEVBCRES_Pos)
8745#define HRTIM_EEFR3_EEVBCRES HRTIM_EEFR3_EEVBCRES_Msk
8746#define HRTIM_EEFR3_EEVBRSTM_Pos (18U)
8747#define HRTIM_EEFR3_EEVBRSTM_Msk (0x1UL << HRTIM_EEFR3_EEVBRSTM_Pos)
8748#define HRTIM_EEFR3_EEVBRSTM HRTIM_EEFR3_EEVBRSTM_Msk
8749#define HRTIM_EEFR3_EEVBSEL_Pos (20U)
8750#define HRTIM_EEFR3_EEVBSEL_Msk (0xFUL << HRTIM_EEFR3_EEVBSEL_Pos)
8751#define HRTIM_EEFR3_EEVBSEL HRTIM_EEFR3_EEVBSEL_Msk
8752#define HRTIM_EEFR3_EEVBSEL_0 (0x1UL << HRTIM_EEFR3_EEVBSEL_Pos)
8753#define HRTIM_EEFR3_EEVBSEL_1 (0x2UL << HRTIM_EEFR3_EEVBSEL_Pos)
8754#define HRTIM_EEFR3_EEVBSEL_2 (0x4UL << HRTIM_EEFR3_EEVBSEL_Pos)
8755#define HRTIM_EEFR3_EEVBSEL_3 (0x8UL << HRTIM_EEFR3_EEVBSEL_Pos)
8756#define HRTIM_EEFR3_EEVBCNT_Pos (24U)
8757#define HRTIM_EEFR3_EEVBCNT_Msk (0x3FUL << HRTIM_EEFR3_EEVBCNT_Pos)
8758#define HRTIM_EEFR3_EEVBCNT HRTIM_EEFR3_EEVBCNT_Msk
8759#define HRTIM_EEFR3_EEVBCNT_0 (0x1UL << HRTIM_EEFR3_EEVBCNT_Pos)
8760#define HRTIM_EEFR3_EEVBCNT_1 (0x2UL << HRTIM_EEFR3_EEVBCNT_Pos)
8761#define HRTIM_EEFR3_EEVBCNT_2 (0x4UL << HRTIM_EEFR3_EEVBCNT_Pos)
8762#define HRTIM_EEFR3_EEVBCNT_3 (0x8UL << HRTIM_EEFR3_EEVBCNT_Pos)
8763#define HRTIM_EEFR3_EEVBCNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos)
8764#define HRTIM_EEFR3_EEVBCNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos)
8766/**** Bit definition for Common HRTIM Timer control register 1 ****************/
8767#define HRTIM_CR1_MUDIS_Pos (0U)
8768#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos)
8769#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk
8770#define HRTIM_CR1_TAUDIS_Pos (1U)
8771#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos)
8772#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk
8773#define HRTIM_CR1_TBUDIS_Pos (2U)
8774#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos)
8775#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk
8776#define HRTIM_CR1_TCUDIS_Pos (3U)
8777#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos)
8778#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk
8779#define HRTIM_CR1_TDUDIS_Pos (4U)
8780#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos)
8781#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk
8782#define HRTIM_CR1_TEUDIS_Pos (5U)
8783#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos)
8784#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk
8785#define HRTIM_CR1_TFUDIS_Pos (6U)
8786#define HRTIM_CR1_TFUDIS_Msk (0x1UL << HRTIM_CR1_TFUDIS_Pos)
8787#define HRTIM_CR1_TFUDIS HRTIM_CR1_TFUDIS_Msk
8788#define HRTIM_CR1_ADC1USRC_Pos (16U)
8789#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos)
8790#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk
8791#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos)
8792#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos)
8793#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos)
8794#define HRTIM_CR1_ADC2USRC_Pos (19U)
8795#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos)
8796#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk
8797#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos)
8798#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos)
8799#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos)
8800#define HRTIM_CR1_ADC3USRC_Pos (22U)
8801#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos)
8802#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk
8803#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos)
8804#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos)
8805#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos)
8806#define HRTIM_CR1_ADC4USRC_Pos (25U)
8807#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos)
8808#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk
8809#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos)
8810#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos)
8811#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos)
8813/**** Bit definition for Common HRTIM Timer control register 2 ****************/
8814#define HRTIM_CR2_MSWU_Pos (0U)
8815#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos)
8816#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk
8817#define HRTIM_CR2_TASWU_Pos (1U)
8818#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos)
8819#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk
8820#define HRTIM_CR2_TBSWU_Pos (2U)
8821#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos)
8822#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk
8823#define HRTIM_CR2_TCSWU_Pos (3U)
8824#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos)
8825#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk
8826#define HRTIM_CR2_TDSWU_Pos (4U)
8827#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos)
8828#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk
8829#define HRTIM_CR2_TESWU_Pos (5U)
8830#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos)
8831#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk
8832#define HRTIM_CR2_TFSWU_Pos (6U)
8833#define HRTIM_CR2_TFSWU_Msk (0x1UL << HRTIM_CR2_TFSWU_Pos)
8834#define HRTIM_CR2_TFSWU HRTIM_CR2_TFSWU_Msk
8835#define HRTIM_CR2_MRST_Pos (8U)
8836#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos)
8837#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk
8838#define HRTIM_CR2_TARST_Pos (9U)
8839#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos)
8840#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk
8841#define HRTIM_CR2_TBRST_Pos (10U)
8842#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos)
8843#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk
8844#define HRTIM_CR2_TCRST_Pos (11U)
8845#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos)
8846#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk
8847#define HRTIM_CR2_TDRST_Pos (12U)
8848#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos)
8849#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk
8850#define HRTIM_CR2_TERST_Pos (13U)
8851#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos)
8852#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk
8853#define HRTIM_CR2_TFRST_Pos (14U)
8854#define HRTIM_CR2_TFRST_Msk (0x1UL << HRTIM_CR2_TFRST_Pos)
8855#define HRTIM_CR2_TFRST HRTIM_CR2_TFRST_Msk
8856#define HRTIM_CR2_SWPA_Pos (16U)
8857#define HRTIM_CR2_SWPA_Msk (0x1UL << HRTIM_CR2_SWPA_Pos)
8858#define HRTIM_CR2_SWPA HRTIM_CR2_SWPA_Msk
8859#define HRTIM_CR2_SWPB_Pos (17U)
8860#define HRTIM_CR2_SWPB_Msk (0x1UL << HRTIM_CR2_SWPB_Pos)
8861#define HRTIM_CR2_SWPB HRTIM_CR2_SWPB_Msk
8862#define HRTIM_CR2_SWPC_Pos (18U)
8863#define HRTIM_CR2_SWPC_Msk (0x1UL << HRTIM_CR2_SWPC_Pos)
8864#define HRTIM_CR2_SWPC HRTIM_CR2_SWPC_Msk
8865#define HRTIM_CR2_SWPD_Pos (19U)
8866#define HRTIM_CR2_SWPD_Msk (0x1UL << HRTIM_CR2_SWPD_Pos)
8867#define HRTIM_CR2_SWPD HRTIM_CR2_SWPD_Msk
8868#define HRTIM_CR2_SWPE_Pos (20U)
8869#define HRTIM_CR2_SWPE_Msk (0x1UL << HRTIM_CR2_SWPE_Pos)
8870#define HRTIM_CR2_SWPE HRTIM_CR2_SWPE_Msk
8871#define HRTIM_CR2_SWPF_Pos (21U)
8872#define HRTIM_CR2_SWPF_Msk (0x1UL << HRTIM_CR2_SWPF_Pos)
8873#define HRTIM_CR2_SWPF HRTIM_CR2_SWPF_Msk
8875/**** Bit definition for Common HRTIM Timer interrupt status register *********/
8876#define HRTIM_ISR_FLT1_Pos (0U)
8877#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos)
8878#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk
8879#define HRTIM_ISR_FLT2_Pos (1U)
8880#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos)
8881#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk
8882#define HRTIM_ISR_FLT3_Pos (2U)
8883#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos)
8884#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk
8885#define HRTIM_ISR_FLT4_Pos (3U)
8886#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos)
8887#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk
8888#define HRTIM_ISR_FLT5_Pos (4U)
8889#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos)
8890#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk
8891#define HRTIM_ISR_SYSFLT_Pos (5U)
8892#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos)
8893#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk
8894#define HRTIM_ISR_FLT6_Pos (6U)
8895#define HRTIM_ISR_FLT6_Msk (0x1UL << HRTIM_ISR_FLT6_Pos)
8896#define HRTIM_ISR_FLT6 HRTIM_ISR_FLT6_Msk
8897#define HRTIM_ISR_DLLRDY_Pos (16U)
8898#define HRTIM_ISR_DLLRDY_Msk (0x1UL << HRTIM_ISR_DLLRDY_Pos)
8899#define HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY_Msk
8900#define HRTIM_ISR_BMPER_Pos (17U)
8901#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos)
8902#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk
8904/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
8905#define HRTIM_ICR_FLT1C_Pos (0U)
8906#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos)
8907#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk
8908#define HRTIM_ICR_FLT2C_Pos (1U)
8909#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos)
8910#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk
8911#define HRTIM_ICR_FLT3C_Pos (2U)
8912#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos)
8913#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk
8914#define HRTIM_ICR_FLT4C_Pos (3U)
8915#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos)
8916#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk
8917#define HRTIM_ICR_FLT5C_Pos (4U)
8918#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos)
8919#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk
8920#define HRTIM_ICR_SYSFLTC_Pos (5U)
8921#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos)
8922#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk
8924#define HRTIM_ICR_FLT6C_Pos (6U)
8925#define HRTIM_ICR_FLT6C_Msk (0x1UL << HRTIM_ICR_FLT6C_Pos)
8926#define HRTIM_ICR_FLT6C HRTIM_ICR_FLT6C_Msk
8928#define HRTIM_ICR_DLLRDYC_Pos (16U)
8929#define HRTIM_ICR_DLLRDYC_Msk (0x1UL << HRTIM_ICR_DLLRDYC_Pos)
8930#define HRTIM_ICR_DLLRDYC HRTIM_ICR_DLLRDYC_Msk
8931#define HRTIM_ICR_BMPERC_Pos (17U)
8932#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos)
8933#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk
8935/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
8936#define HRTIM_IER_FLT1_Pos (0U)
8937#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos)
8938#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk
8939#define HRTIM_IER_FLT2_Pos (1U)
8940#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos)
8941#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk
8942#define HRTIM_IER_FLT3_Pos (2U)
8943#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos)
8944#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk
8945#define HRTIM_IER_FLT4_Pos (3U)
8946#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos)
8947#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk
8948#define HRTIM_IER_FLT5_Pos (4U)
8949#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos)
8950#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk
8951#define HRTIM_IER_SYSFLT_Pos (5U)
8952#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos)
8953#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk
8954#define HRTIM_IER_FLT6_Pos (6U)
8955#define HRTIM_IER_FLT6_Msk (0x1UL << HRTIM_IER_FLT6_Pos)
8956#define HRTIM_IER_FLT6 HRTIM_IER_FLT6_Msk
8958#define HRTIM_IER_DLLRDY_Pos (16U)
8959#define HRTIM_IER_DLLRDY_Msk (0x1UL << HRTIM_IER_DLLRDY_Pos)
8960#define HRTIM_IER_DLLRDY HRTIM_IER_DLLRDY_Msk
8961#define HRTIM_IER_BMPER_Pos (17U)
8962#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos)
8963#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk
8965/**** Bit definition for Common HRTIM Timer output enable register ************/
8966#define HRTIM_OENR_TA1OEN_Pos (0U)
8967#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos)
8968#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk
8969#define HRTIM_OENR_TA2OEN_Pos (1U)
8970#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos)
8971#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk
8972#define HRTIM_OENR_TB1OEN_Pos (2U)
8973#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos)
8974#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk
8975#define HRTIM_OENR_TB2OEN_Pos (3U)
8976#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos)
8977#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk
8978#define HRTIM_OENR_TC1OEN_Pos (4U)
8979#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos)
8980#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk
8981#define HRTIM_OENR_TC2OEN_Pos (5U)
8982#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos)
8983#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk
8984#define HRTIM_OENR_TD1OEN_Pos (6U)
8985#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos)
8986#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk
8987#define HRTIM_OENR_TD2OEN_Pos (7U)
8988#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos)
8989#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk
8990#define HRTIM_OENR_TE1OEN_Pos (8U)
8991#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos)
8992#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk
8993#define HRTIM_OENR_TE2OEN_Pos (9U)
8994#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos)
8995#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk
8996#define HRTIM_OENR_TF1OEN_Pos (10U)
8997#define HRTIM_OENR_TF1OEN_Msk (0x1UL << HRTIM_OENR_TF1OEN_Pos)
8998#define HRTIM_OENR_TF1OEN HRTIM_OENR_TF1OEN_Msk
8999#define HRTIM_OENR_TF2OEN_Pos (11U)
9000#define HRTIM_OENR_TF2OEN_Msk (0x1UL << HRTIM_OENR_TF2OEN_Pos)
9001#define HRTIM_OENR_TF2OEN HRTIM_OENR_TF2OEN_Msk
9003/**** Bit definition for Common HRTIM Timer output disable register ***********/
9004#define HRTIM_ODISR_TA1ODIS_Pos (0U)
9005#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)
9006#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk
9007#define HRTIM_ODISR_TA2ODIS_Pos (1U)
9008#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)
9009#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk
9010#define HRTIM_ODISR_TB1ODIS_Pos (2U)
9011#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)
9012#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk
9013#define HRTIM_ODISR_TB2ODIS_Pos (3U)
9014#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)
9015#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk
9016#define HRTIM_ODISR_TC1ODIS_Pos (4U)
9017#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)
9018#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk
9019#define HRTIM_ODISR_TC2ODIS_Pos (5U)
9020#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)
9021#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk
9022#define HRTIM_ODISR_TD1ODIS_Pos (6U)
9023#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)
9024#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk
9025#define HRTIM_ODISR_TD2ODIS_Pos (7U)
9026#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)
9027#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk
9028#define HRTIM_ODISR_TE1ODIS_Pos (8U)
9029#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)
9030#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk
9031#define HRTIM_ODISR_TE2ODIS_Pos (9U)
9032#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)
9033#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk
9034#define HRTIM_ODISR_TF1ODIS_Pos (10U)
9035#define HRTIM_ODISR_TF1ODIS_Msk (0x1UL << HRTIM_ODISR_TF1ODIS_Pos)
9036#define HRTIM_ODISR_TF1ODIS HRTIM_ODISR_TF1ODIS_Msk
9037#define HRTIM_ODISR_TF2ODIS_Pos (11U)
9038#define HRTIM_ODISR_TF2ODIS_Msk (0x1UL << HRTIM_ODISR_TF2ODIS_Pos)
9039#define HRTIM_ODISR_TF2ODIS HRTIM_ODISR_TF2ODIS_Msk
9041/**** Bit definition for Common HRTIM Timer output disable status register *****/
9042#define HRTIM_ODSR_TA1ODS_Pos (0U)
9043#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos)
9044#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk
9045#define HRTIM_ODSR_TA2ODS_Pos (1U)
9046#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos)
9047#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk
9048#define HRTIM_ODSR_TB1ODS_Pos (2U)
9049#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos)
9050#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk
9051#define HRTIM_ODSR_TB2ODS_Pos (3U)
9052#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos)
9053#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk
9054#define HRTIM_ODSR_TC1ODS_Pos (4U)
9055#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos)
9056#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk
9057#define HRTIM_ODSR_TC2ODS_Pos (5U)
9058#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos)
9059#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk
9060#define HRTIM_ODSR_TD1ODS_Pos (6U)
9061#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos)
9062#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk
9063#define HRTIM_ODSR_TD2ODS_Pos (7U)
9064#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos)
9065#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk
9066#define HRTIM_ODSR_TE1ODS_Pos (8U)
9067#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos)
9068#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk
9069#define HRTIM_ODSR_TE2ODS_Pos (9U)
9070#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos)
9071#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk
9072#define HRTIM_ODSR_TF1ODS_Pos (10U)
9073#define HRTIM_ODSR_TF1ODS_Msk (0x1UL << HRTIM_ODSR_TF1ODS_Pos)
9074#define HRTIM_ODSR_TF1ODS HRTIM_ODSR_TF1ODS_Msk
9075#define HRTIM_ODSR_TF2ODS_Pos (11U)
9076#define HRTIM_ODSR_TF2ODS_Msk (0x1UL << HRTIM_ODSR_TF2ODS_Pos)
9077#define HRTIM_ODSR_TF2ODS HRTIM_ODSR_TF2ODS_Msk
9079/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
9080#define HRTIM_BMCR_BME_Pos (0U)
9081#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos)
9082#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk
9083#define HRTIM_BMCR_BMOM_Pos (1U)
9084#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos)
9085#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk
9086#define HRTIM_BMCR_BMCLK_Pos (2U)
9087#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos)
9088#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk
9089#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos)
9090#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos)
9091#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos)
9092#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos)
9093#define HRTIM_BMCR_BMPRSC_Pos (6U)
9094#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos)
9095#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk
9096#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos)
9097#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos)
9098#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos)
9099#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos)
9100#define HRTIM_BMCR_BMPREN_Pos (10U)
9101#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos)
9102#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk
9103#define HRTIM_BMCR_MTBM_Pos (16U)
9104#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos)
9105#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk
9106#define HRTIM_BMCR_TABM_Pos (17U)
9107#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos)
9108#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk
9109#define HRTIM_BMCR_TBBM_Pos (18U)
9110#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos)
9111#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk
9112#define HRTIM_BMCR_TCBM_Pos (19U)
9113#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos)
9114#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk
9115#define HRTIM_BMCR_TDBM_Pos (20U)
9116#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos)
9117#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk
9118#define HRTIM_BMCR_TEBM_Pos (21U)
9119#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos)
9120#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk
9122#define HRTIM_BMCR_TFBM_Pos (22U)
9123#define HRTIM_BMCR_TFBM_Msk (0x1UL << HRTIM_BMCR_TFBM_Pos)
9124#define HRTIM_BMCR_TFBM HRTIM_BMCR_TFBM_Msk
9126#define HRTIM_BMCR_BMSTAT_Pos (31U)
9127#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos)
9128#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk
9130/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
9131#define HRTIM_BMTRGR_SW_Pos (0U)
9132#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos)
9133#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk
9134#define HRTIM_BMTRGR_MSTRST_Pos (1U)
9135#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)
9136#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk
9137#define HRTIM_BMTRGR_MSTREP_Pos (2U)
9138#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)
9139#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk
9140#define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
9141#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)
9142#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk
9143#define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
9144#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)
9145#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk
9146#define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
9147#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)
9148#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk
9149#define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
9150#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)
9151#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk
9152#define HRTIM_BMTRGR_TARST_Pos (7U)
9153#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos)
9154#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk
9155#define HRTIM_BMTRGR_TAREP_Pos (8U)
9156#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos)
9157#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk
9158#define HRTIM_BMTRGR_TACMP1_Pos (9U)
9159#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)
9160#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk
9161#define HRTIM_BMTRGR_TACMP2_Pos (10U)
9162#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)
9163#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk
9164#define HRTIM_BMTRGR_TBRST_Pos (11U)
9165#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos)
9166#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk
9167#define HRTIM_BMTRGR_TBREP_Pos (12U)
9168#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos)
9169#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk
9170#define HRTIM_BMTRGR_TBCMP1_Pos (13U)
9171#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)
9172#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk
9173#define HRTIM_BMTRGR_TBCMP2_Pos (14U)
9174#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)
9175#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk
9176#define HRTIM_BMTRGR_TCRST_Pos (15U)
9177#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos)
9178#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk
9179#define HRTIM_BMTRGR_TCREP_Pos (16U)
9180#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos)
9181#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk
9182#define HRTIM_BMTRGR_TCCMP1_Pos (17U)
9183#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)
9184#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk
9185#define HRTIM_BMTRGR_TFRST_Pos (18U)
9186#define HRTIM_BMTRGR_TFRST_Msk (0x1UL << HRTIM_BMTRGR_TFRST_Pos)
9187#define HRTIM_BMTRGR_TFRST HRTIM_BMTRGR_TFRST_Msk
9188#define HRTIM_BMTRGR_TDRST_Pos (19U)
9189#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos)
9190#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk
9191#define HRTIM_BMTRGR_TDREP_Pos (20U)
9192#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos)
9193#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk
9194#define HRTIM_BMTRGR_TFREP_Pos (21U)
9195#define HRTIM_BMTRGR_TFREP_Msk (0x1UL << HRTIM_BMTRGR_TFREP_Pos)
9196#define HRTIM_BMTRGR_TFREP HRTIM_BMTRGR_TFREP_Msk
9197#define HRTIM_BMTRGR_TDCMP2_Pos (22U)
9198#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)
9199#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk
9200#define HRTIM_BMTRGR_TFCMP1_Pos (23U)
9201#define HRTIM_BMTRGR_TFCMP1_Msk (0x1UL << HRTIM_BMTRGR_TFCMP1_Pos)
9202#define HRTIM_BMTRGR_TFCMP1 HRTIM_BMTRGR_TFCMP1_Msk
9203#define HRTIM_BMTRGR_TEREP_Pos (24U)
9204#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos)
9205#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk
9206#define HRTIM_BMTRGR_TECMP1_Pos (25U)
9207#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)
9208#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk
9209#define HRTIM_BMTRGR_TECMP2_Pos (26U)
9210#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)
9211#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk
9212#define HRTIM_BMTRGR_TAEEV7_Pos (27U)
9213#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)
9214#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk
9215#define HRTIM_BMTRGR_TDEEV8_Pos (28U)
9216#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)
9217#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk
9218#define HRTIM_BMTRGR_EEV7_Pos (29U)
9219#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos)
9220#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk
9221#define HRTIM_BMTRGR_EEV8_Pos (30U)
9222#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos)
9223#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk
9224#define HRTIM_BMTRGR_OCHPEV_Pos (31U)
9225#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)
9226#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk
9228/******************* Bit definition for HRTIM_BMCMPR register ***************/
9229#define HRTIM_BMCMPR_BMCMPR_Pos (0U)
9230#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)
9231#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk
9233/******************* Bit definition for HRTIM_BMPER register ****************/
9234#define HRTIM_BMPER_BMPER_Pos (0U)
9235#define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)
9236#define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk
9238/******************* Bit definition for HRTIM_EECR1 register ****************/
9239#define HRTIM_EECR1_EE1SRC_Pos (0U)
9240#define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos)
9241#define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk
9242#define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos)
9243#define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos)
9244#define HRTIM_EECR1_EE1POL_Pos (2U)
9245#define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos)
9246#define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk
9247#define HRTIM_EECR1_EE1SNS_Pos (3U)
9248#define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos)
9249#define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk
9250#define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos)
9251#define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos)
9252#define HRTIM_EECR1_EE1FAST_Pos (5U)
9253#define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos)
9254#define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk
9256#define HRTIM_EECR1_EE2SRC_Pos (6U)
9257#define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos)
9258#define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk
9259#define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos)
9260#define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos)
9261#define HRTIM_EECR1_EE2POL_Pos (8U)
9262#define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos)
9263#define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk
9264#define HRTIM_EECR1_EE2SNS_Pos (9U)
9265#define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos)
9266#define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk
9267#define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos)
9268#define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos)
9269#define HRTIM_EECR1_EE2FAST_Pos (11U)
9270#define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos)
9271#define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk
9273#define HRTIM_EECR1_EE3SRC_Pos (12U)
9274#define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos)
9275#define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk
9276#define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos)
9277#define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos)
9278#define HRTIM_EECR1_EE3POL_Pos (14U)
9279#define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos)
9280#define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk
9281#define HRTIM_EECR1_EE3SNS_Pos (15U)
9282#define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos)
9283#define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk
9284#define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos)
9285#define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos)
9286#define HRTIM_EECR1_EE3FAST_Pos (17U)
9287#define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos)
9288#define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk
9290#define HRTIM_EECR1_EE4SRC_Pos (18U)
9291#define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos)
9292#define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk
9293#define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos)
9294#define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos)
9295#define HRTIM_EECR1_EE4POL_Pos (20U)
9296#define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos)
9297#define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk
9298#define HRTIM_EECR1_EE4SNS_Pos (21U)
9299#define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos)
9300#define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk
9301#define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos)
9302#define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos)
9303#define HRTIM_EECR1_EE4FAST_Pos (23U)
9304#define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos)
9305#define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk
9307#define HRTIM_EECR1_EE5SRC_Pos (24U)
9308#define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos)
9309#define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk
9310#define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos)
9311#define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos)
9312#define HRTIM_EECR1_EE5POL_Pos (26U)
9313#define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos)
9314#define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk
9315#define HRTIM_EECR1_EE5SNS_Pos (27U)
9316#define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos)
9317#define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk
9318#define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos)
9319#define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos)
9320#define HRTIM_EECR1_EE5FAST_Pos (29U)
9321#define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos)
9322#define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk
9324/******************* Bit definition for HRTIM_EECR2 register ****************/
9325#define HRTIM_EECR2_EE6SRC_Pos (0U)
9326#define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos)
9327#define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk
9328#define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos)
9329#define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos)
9330#define HRTIM_EECR2_EE6POL_Pos (2U)
9331#define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos)
9332#define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk
9333#define HRTIM_EECR2_EE6SNS_Pos (3U)
9334#define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos)
9335#define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk
9336#define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos)
9337#define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos)
9339#define HRTIM_EECR2_EE7SRC_Pos (6U)
9340#define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos)
9341#define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk
9342#define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos)
9343#define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos)
9344#define HRTIM_EECR2_EE7POL_Pos (8U)
9345#define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos)
9346#define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk
9347#define HRTIM_EECR2_EE7SNS_Pos (9U)
9348#define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos)
9349#define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk
9350#define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos)
9351#define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos)
9353#define HRTIM_EECR2_EE8SRC_Pos (12U)
9354#define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos)
9355#define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk
9356#define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos)
9357#define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos)
9358#define HRTIM_EECR2_EE8POL_Pos (14U)
9359#define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos)
9360#define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk
9361#define HRTIM_EECR2_EE8SNS_Pos (15U)
9362#define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos)
9363#define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk
9364#define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos)
9365#define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos)
9367#define HRTIM_EECR2_EE9SRC_Pos (18U)
9368#define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos)
9369#define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk
9370#define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos)
9371#define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos)
9372#define HRTIM_EECR2_EE9POL_Pos (20U)
9373#define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos)
9374#define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk
9375#define HRTIM_EECR2_EE9SNS_Pos (21U)
9376#define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos)
9377#define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk
9378#define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos)
9379#define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos)
9381#define HRTIM_EECR2_EE10SRC_Pos (24U)
9382#define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos)
9383#define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk
9384#define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos)
9385#define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos)
9386#define HRTIM_EECR2_EE10POL_Pos (26U)
9387#define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos)
9388#define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk
9389#define HRTIM_EECR2_EE10SNS_Pos (27U)
9390#define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos)
9391#define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk
9392#define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos)
9393#define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos)
9395/******************* Bit definition for HRTIM_EECR3 register ****************/
9396#define HRTIM_EECR3_EE6F_Pos (0U)
9397#define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos)
9398#define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk
9399#define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos)
9400#define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos)
9401#define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos)
9402#define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos)
9403#define HRTIM_EECR3_EE7F_Pos (6U)
9404#define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos)
9405#define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk
9406#define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos)
9407#define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos)
9408#define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos)
9409#define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos)
9410#define HRTIM_EECR3_EE8F_Pos (12U)
9411#define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos)
9412#define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk
9413#define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos)
9414#define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos)
9415#define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos)
9416#define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos)
9417#define HRTIM_EECR3_EE9F_Pos (18U)
9418#define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos)
9419#define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk
9420#define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos)
9421#define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos)
9422#define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos)
9423#define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos)
9424#define HRTIM_EECR3_EE10F_Pos (24U)
9425#define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos)
9426#define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk
9427#define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos)
9428#define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos)
9429#define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos)
9430#define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos)
9431#define HRTIM_EECR3_EEVSD_Pos (30U)
9432#define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos)
9433#define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk
9434#define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos)
9435#define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos)
9437/******************* Bit definition for HRTIM_ADC1R register ****************/
9438#define HRTIM_ADC1R_AD1MC1_Pos (0U)
9439#define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)
9440#define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk
9441#define HRTIM_ADC1R_AD1MC2_Pos (1U)
9442#define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)
9443#define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk
9444#define HRTIM_ADC1R_AD1MC3_Pos (2U)
9445#define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)
9446#define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk
9447#define HRTIM_ADC1R_AD1MC4_Pos (3U)
9448#define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)
9449#define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk
9450#define HRTIM_ADC1R_AD1MPER_Pos (4U)
9451#define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)
9452#define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk
9453#define HRTIM_ADC1R_AD1EEV1_Pos (5U)
9454#define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)
9455#define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk
9456#define HRTIM_ADC1R_AD1EEV2_Pos (6U)
9457#define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)
9458#define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk
9459#define HRTIM_ADC1R_AD1EEV3_Pos (7U)
9460#define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)
9461#define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk
9462#define HRTIM_ADC1R_AD1EEV4_Pos (8U)
9463#define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)
9464#define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk
9465#define HRTIM_ADC1R_AD1EEV5_Pos (9U)
9466#define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)
9467#define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk
9469#define HRTIM_ADC1R_AD1TFC2_Pos (10U)
9470#define HRTIM_ADC1R_AD1TFC2_Msk (0x1UL << HRTIM_ADC1R_AD1TFC2_Pos)
9471#define HRTIM_ADC1R_AD1TFC2 HRTIM_ADC1R_AD1TFC2_Msk
9473#define HRTIM_ADC1R_AD1TAC3_Pos (11U)
9474#define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)
9475#define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk
9476#define HRTIM_ADC1R_AD1TAC4_Pos (12U)
9477#define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)
9478#define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk
9479#define HRTIM_ADC1R_AD1TAPER_Pos (13U)
9480#define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)
9481#define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk
9482#define HRTIM_ADC1R_AD1TARST_Pos (14U)
9483#define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)
9484#define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk
9486#define HRTIM_ADC1R_AD1TFC3_Pos (15U)
9487#define HRTIM_ADC1R_AD1TFC3_Msk (0x1UL << HRTIM_ADC1R_AD1TFC3_Pos)
9488#define HRTIM_ADC1R_AD1TFC3 HRTIM_ADC1R_AD1TFC3_Msk
9490#define HRTIM_ADC1R_AD1TBC3_Pos (16U)
9491#define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)
9492#define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk
9493#define HRTIM_ADC1R_AD1TBC4_Pos (17U)
9494#define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)
9495#define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk
9496#define HRTIM_ADC1R_AD1TBPER_Pos (18U)
9497#define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)
9498#define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk
9499#define HRTIM_ADC1R_AD1TBRST_Pos (19U)
9500#define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)
9501#define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk
9503#define HRTIM_ADC1R_AD1TFC4_Pos (20U)
9504#define HRTIM_ADC1R_AD1TFC4_Msk (0x1UL << HRTIM_ADC1R_AD1TFC4_Pos)
9505#define HRTIM_ADC1R_AD1TFC4 HRTIM_ADC1R_AD1TFC4_Msk
9507#define HRTIM_ADC1R_AD1TCC3_Pos (21U)
9508#define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)
9509#define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk
9510#define HRTIM_ADC1R_AD1TCC4_Pos (22U)
9511#define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)
9512#define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk
9513#define HRTIM_ADC1R_AD1TCPER_Pos (23U)
9514#define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)
9515#define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk
9517#define HRTIM_ADC1R_AD1TFPER_Pos (24U)
9518#define HRTIM_ADC1R_AD1TFPER_Msk (0x1UL << HRTIM_ADC1R_AD1TFPER_Pos)
9519#define HRTIM_ADC1R_AD1TFPER HRTIM_ADC1R_AD1TFPER_Msk
9521#define HRTIM_ADC1R_AD1TDC3_Pos (25U)
9522#define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)
9523#define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk
9524#define HRTIM_ADC1R_AD1TDC4_Pos (26U)
9525#define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)
9526#define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk
9527#define HRTIM_ADC1R_AD1TDPER_Pos (27U)
9528#define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)
9529#define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk
9531#define HRTIM_ADC1R_AD1TFRST_Pos (28U)
9532#define HRTIM_ADC1R_AD1TFRST_Msk (0x1UL << HRTIM_ADC1R_AD1TFRST_Pos)
9533#define HRTIM_ADC1R_AD1TFRST HRTIM_ADC1R_AD1TFRST_Msk
9535#define HRTIM_ADC1R_AD1TEC3_Pos (29U)
9536#define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)
9537#define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk
9538#define HRTIM_ADC1R_AD1TEC4_Pos (30U)
9539#define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)
9540#define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk
9541#define HRTIM_ADC1R_AD1TEPER_Pos (31U)
9542#define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)
9543#define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk
9545/******************* Bit definition for HRTIM_ADC2R register ****************/
9546#define HRTIM_ADC2R_AD2MC1_Pos (0U)
9547#define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)
9548#define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk
9549#define HRTIM_ADC2R_AD2MC2_Pos (1U)
9550#define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)
9551#define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk
9552#define HRTIM_ADC2R_AD2MC3_Pos (2U)
9553#define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)
9554#define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk
9555#define HRTIM_ADC2R_AD2MC4_Pos (3U)
9556#define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)
9557#define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk
9558#define HRTIM_ADC2R_AD2MPER_Pos (4U)
9559#define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)
9560#define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk
9561#define HRTIM_ADC2R_AD2EEV6_Pos (5U)
9562#define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)
9563#define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk
9564#define HRTIM_ADC2R_AD2EEV7_Pos (6U)
9565#define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)
9566#define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk
9567#define HRTIM_ADC2R_AD2EEV8_Pos (7U)
9568#define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)
9569#define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk
9570#define HRTIM_ADC2R_AD2EEV9_Pos (8U)
9571#define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)
9572#define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk
9573#define HRTIM_ADC2R_AD2EEV10_Pos (9U)
9574#define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)
9575#define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk
9576#define HRTIM_ADC2R_AD2TAC2_Pos (10U)
9577#define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)
9578#define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk
9580#define HRTIM_ADC2R_AD2TFC2_Pos (11U)
9581#define HRTIM_ADC2R_AD2TFC2_Msk (0x1UL << HRTIM_ADC2R_AD2TFC2_Pos)
9582#define HRTIM_ADC2R_AD2TFC2 HRTIM_ADC2R_AD2TFC2_Msk
9584#define HRTIM_ADC2R_AD2TAC4_Pos (12U)
9585#define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)
9586#define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk
9587#define HRTIM_ADC2R_AD2TAPER_Pos (13U)
9588#define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)
9589#define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk
9590#define HRTIM_ADC2R_AD2TBC2_Pos (14U)
9591#define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)
9592#define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk
9594#define HRTIM_ADC2R_AD2TFC3_Pos (15U)
9595#define HRTIM_ADC2R_AD2TFC3_Msk (0x1UL << HRTIM_ADC2R_AD2TFC3_Pos)
9596#define HRTIM_ADC2R_AD2TFC3 HRTIM_ADC2R_AD2TFC3_Msk
9598#define HRTIM_ADC2R_AD2TBC4_Pos (16U)
9599#define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)
9600#define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk
9601#define HRTIM_ADC2R_AD2TBPER_Pos (17U)
9602#define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)
9603#define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk
9604#define HRTIM_ADC2R_AD2TCC2_Pos (18U)
9605#define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)
9606#define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk
9608#define HRTIM_ADC2R_AD2TFC4_Pos (19U)
9609#define HRTIM_ADC2R_AD2TFC4_Msk (0x1UL << HRTIM_ADC2R_AD2TFC4_Pos)
9610#define HRTIM_ADC2R_AD2TFC4 HRTIM_ADC2R_AD2TFC4_Msk
9612#define HRTIM_ADC2R_AD2TCC4_Pos (20U)
9613#define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)
9614#define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk
9615#define HRTIM_ADC2R_AD2TCPER_Pos (21U)
9616#define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)
9617#define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk
9618#define HRTIM_ADC2R_AD2TCRST_Pos (22U)
9619#define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)
9620#define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk
9621#define HRTIM_ADC2R_AD2TDC2_Pos (23U)
9622#define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)
9623#define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk
9625#define HRTIM_ADC2R_AD2TFPER_Pos (24U)
9626#define HRTIM_ADC2R_AD2TFPER_Msk (0x1UL << HRTIM_ADC2R_AD2TFPER_Pos)
9627#define HRTIM_ADC2R_AD2TFPER HRTIM_ADC2R_AD2TFPER_Msk
9629#define HRTIM_ADC2R_AD2TDC4_Pos (25U)
9630#define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)
9631#define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk
9632#define HRTIM_ADC2R_AD2TDPER_Pos (26U)
9633#define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)
9634#define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk
9635#define HRTIM_ADC2R_AD2TDRST_Pos (27U)
9636#define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)
9637#define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk
9638#define HRTIM_ADC2R_AD2TEC2_Pos (28U)
9639#define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)
9640#define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk
9641#define HRTIM_ADC2R_AD2TEC3_Pos (29U)
9642#define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)
9643#define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk
9644#define HRTIM_ADC2R_AD2TEC4_Pos (30U)
9645#define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)
9646#define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk
9647#define HRTIM_ADC2R_AD2TERST_Pos (31U)
9648#define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)
9649#define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk
9651/******************* Bit definition for HRTIM_ADC3R register ****************/
9652#define HRTIM_ADC3R_AD3MC1_Pos (0U)
9653#define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)
9654#define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk
9655#define HRTIM_ADC3R_AD3MC2_Pos (1U)
9656#define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)
9657#define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk
9658#define HRTIM_ADC3R_AD3MC3_Pos (2U)
9659#define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)
9660#define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk
9661#define HRTIM_ADC3R_AD3MC4_Pos (3U)
9662#define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)
9663#define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk
9664#define HRTIM_ADC3R_AD3MPER_Pos (4U)
9665#define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)
9666#define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk
9667#define HRTIM_ADC3R_AD3EEV1_Pos (5U)
9668#define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)
9669#define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk
9670#define HRTIM_ADC3R_AD3EEV2_Pos (6U)
9671#define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)
9672#define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk
9673#define HRTIM_ADC3R_AD3EEV3_Pos (7U)
9674#define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)
9675#define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk
9676#define HRTIM_ADC3R_AD3EEV4_Pos (8U)
9677#define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)
9678#define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk
9679#define HRTIM_ADC3R_AD3EEV5_Pos (9U)
9680#define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)
9681#define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk
9683#define HRTIM_ADC3R_AD3TFC2_Pos (10U)
9684#define HRTIM_ADC3R_AD3TFC2_Msk (0x1UL << HRTIM_ADC3R_AD3TFC2_Pos)
9685#define HRTIM_ADC3R_AD3TFC2 HRTIM_ADC3R_AD3TFC2_Msk
9687#define HRTIM_ADC3R_AD3TAC3_Pos (11U)
9688#define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)
9689#define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk
9690#define HRTIM_ADC3R_AD3TAC4_Pos (12U)
9691#define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)
9692#define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk
9693#define HRTIM_ADC3R_AD3TAPER_Pos (13U)
9694#define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)
9695#define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk
9696#define HRTIM_ADC3R_AD3TARST_Pos (14U)
9697#define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)
9698#define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk
9700#define HRTIM_ADC3R_AD3TFC3_Pos (15U)
9701#define HRTIM_ADC3R_AD3TFC3_Msk (0x1UL << HRTIM_ADC3R_AD3TFC3_Pos)
9702#define HRTIM_ADC3R_AD3TFC3 HRTIM_ADC3R_AD3TFC3_Msk
9704#define HRTIM_ADC3R_AD3TBC3_Pos (16U)
9705#define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)
9706#define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk
9707#define HRTIM_ADC3R_AD3TBC4_Pos (17U)
9708#define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)
9709#define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk
9710#define HRTIM_ADC3R_AD3TBPER_Pos (18U)
9711#define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)
9712#define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk
9713#define HRTIM_ADC3R_AD3TBRST_Pos (19U)
9714#define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)
9715#define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk
9717#define HRTIM_ADC3R_AD3TFC4_Pos (20U)
9718#define HRTIM_ADC3R_AD3TFC4_Msk (0x1UL << HRTIM_ADC3R_AD3TFC4_Pos)
9719#define HRTIM_ADC3R_AD3TFC4 HRTIM_ADC3R_AD3TFC4_Msk
9721#define HRTIM_ADC3R_AD3TCC3_Pos (21U)
9722#define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)
9723#define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk
9724#define HRTIM_ADC3R_AD3TCC4_Pos (22U)
9725#define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)
9726#define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk
9727#define HRTIM_ADC3R_AD3TCPER_Pos (23U)
9728#define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)
9729#define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk
9731#define HRTIM_ADC3R_AD3TFPER_Pos (24U)
9732#define HRTIM_ADC3R_AD3TFPER_Msk (0x1UL << HRTIM_ADC3R_AD3TFPER_Pos)
9733#define HRTIM_ADC3R_AD3TFPER HRTIM_ADC3R_AD3TFPER_Msk
9735#define HRTIM_ADC3R_AD3TDC3_Pos (25U)
9736#define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)
9737#define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk
9738#define HRTIM_ADC3R_AD3TDC4_Pos (26U)
9739#define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)
9740#define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk
9741#define HRTIM_ADC3R_AD3TDPER_Pos (27U)
9742#define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)
9743#define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk
9745#define HRTIM_ADC3R_AD3TFRST_Pos (28U)
9746#define HRTIM_ADC3R_AD3TFRST_Msk (0x1UL << HRTIM_ADC3R_AD3TFRST_Pos)
9747#define HRTIM_ADC3R_AD3TFRST HRTIM_ADC3R_AD3TFRST_Msk
9749#define HRTIM_ADC3R_AD3TEC3_Pos (29U)
9750#define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)
9751#define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk
9752#define HRTIM_ADC3R_AD3TEC4_Pos (30U)
9753#define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)
9754#define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk
9755#define HRTIM_ADC3R_AD3TEPER_Pos (31U)
9756#define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)
9757#define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk
9759/******************* Bit definition for HRTIM_ADC4R register ****************/
9760#define HRTIM_ADC4R_AD4MC1_Pos (0U)
9761#define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)
9762#define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk
9763#define HRTIM_ADC4R_AD4MC2_Pos (1U)
9764#define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)
9765#define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk
9766#define HRTIM_ADC4R_AD4MC3_Pos (2U)
9767#define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)
9768#define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk
9769#define HRTIM_ADC4R_AD4MC4_Pos (3U)
9770#define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)
9771#define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk
9772#define HRTIM_ADC4R_AD4MPER_Pos (4U)
9773#define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)
9774#define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk
9775#define HRTIM_ADC4R_AD4EEV6_Pos (5U)
9776#define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)
9777#define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk
9778#define HRTIM_ADC4R_AD4EEV7_Pos (6U)
9779#define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)
9780#define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk
9781#define HRTIM_ADC4R_AD4EEV8_Pos (7U)
9782#define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)
9783#define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk
9784#define HRTIM_ADC4R_AD4EEV9_Pos (8U)
9785#define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)
9786#define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk
9787#define HRTIM_ADC4R_AD4EEV10_Pos (9U)
9788#define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)
9789#define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk
9790#define HRTIM_ADC4R_AD4TAC2_Pos (10U)
9791#define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)
9792#define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk
9794#define HRTIM_ADC4R_AD4TFC2_Pos (11U)
9795#define HRTIM_ADC4R_AD4TFC2_Msk (0x1UL << HRTIM_ADC4R_AD4TFC2_Pos)
9796#define HRTIM_ADC4R_AD4TFC2 HRTIM_ADC4R_AD4TFC2_Msk
9798#define HRTIM_ADC4R_AD4TAC4_Pos (12U)
9799#define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)
9800#define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk
9801#define HRTIM_ADC4R_AD4TAPER_Pos (13U)
9802#define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)
9803#define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk
9804#define HRTIM_ADC4R_AD4TBC2_Pos (14U)
9805#define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)
9806#define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk
9808#define HRTIM_ADC4R_AD4TFC3_Pos (15U)
9809#define HRTIM_ADC4R_AD4TFC3_Msk (0x1UL << HRTIM_ADC4R_AD4TFC3_Pos)
9810#define HRTIM_ADC4R_AD4TFC3 HRTIM_ADC4R_AD4TFC3_Msk
9812#define HRTIM_ADC4R_AD4TBC4_Pos (16U)
9813#define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)
9814#define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk
9815#define HRTIM_ADC4R_AD4TBPER_Pos (17U)
9816#define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)
9817#define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk
9818#define HRTIM_ADC4R_AD4TCC2_Pos (18U)
9819#define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)
9820#define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk
9822#define HRTIM_ADC4R_AD4TFC4_Pos (19U)
9823#define HRTIM_ADC4R_AD4TFC4_Msk (0x1UL << HRTIM_ADC4R_AD4TFC4_Pos)
9824#define HRTIM_ADC4R_AD4TFC4 HRTIM_ADC4R_AD4TFC4_Msk
9826#define HRTIM_ADC4R_AD4TCC4_Pos (20U)
9827#define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)
9828#define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk
9829#define HRTIM_ADC4R_AD4TCPER_Pos (21U)
9830#define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)
9831#define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk
9832#define HRTIM_ADC4R_AD4TCRST_Pos (22U)
9833#define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)
9834#define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk
9835#define HRTIM_ADC4R_AD4TDC2_Pos (23U)
9836#define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)
9837#define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk
9839#define HRTIM_ADC4R_AD4TFPER_Pos (24U)
9840#define HRTIM_ADC4R_AD4TFPER_Msk (0x1UL << HRTIM_ADC4R_AD4TFPER_Pos)
9841#define HRTIM_ADC4R_AD4TFPER HRTIM_ADC4R_AD4TFPER_Msk
9843#define HRTIM_ADC4R_AD4TDC4_Pos (25U)
9844#define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)
9845#define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk
9846#define HRTIM_ADC4R_AD4TDPER_Pos (26U)
9847#define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)
9848#define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk
9849#define HRTIM_ADC4R_AD4TDRST_Pos (27U)
9850#define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)
9851#define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk
9852#define HRTIM_ADC4R_AD4TEC2_Pos (28U)
9853#define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)
9854#define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk
9855#define HRTIM_ADC4R_AD4TEC3_Pos (29U)
9856#define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)
9857#define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk
9858#define HRTIM_ADC4R_AD4TEC4_Pos (30U)
9859#define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)
9860#define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk
9861#define HRTIM_ADC4R_AD4TERST_Pos (31U)
9862#define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)
9863#define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk
9865/******************* Bit definition for HRTIM_DLLCR register ****************/
9866#define HRTIM_DLLCR_CAL_Pos (0U)
9867#define HRTIM_DLLCR_CAL_Msk (0x1UL << HRTIM_DLLCR_CAL_Pos)
9868#define HRTIM_DLLCR_CAL HRTIM_DLLCR_CAL_Msk
9869#define HRTIM_DLLCR_CALEN_Pos (1U)
9870#define HRTIM_DLLCR_CALEN_Msk (0x1UL << HRTIM_DLLCR_CALEN_Pos)
9871#define HRTIM_DLLCR_CALEN HRTIM_DLLCR_CALEN_Msk
9872#define HRTIM_DLLCR_CALRTE_Pos (2U)
9873#define HRTIM_DLLCR_CALRTE_Msk (0x3UL << HRTIM_DLLCR_CALRTE_Pos)
9874#define HRTIM_DLLCR_CALRTE HRTIM_DLLCR_CALRTE_Msk
9875#define HRTIM_DLLCR_CALRTE_0 (0x1UL << HRTIM_DLLCR_CALRTE_Pos)
9876#define HRTIM_DLLCR_CALRTE_1 (0x2UL << HRTIM_DLLCR_CALRTE_Pos)
9878/******************* Bit definition for HRTIM_FLTINR1 register ***************/
9879#define HRTIM_FLTINR1_FLT1E_Pos (0U)
9880#define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)
9881#define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk
9882#define HRTIM_FLTINR1_FLT1P_Pos (1U)
9883#define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)
9884#define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk
9885#define HRTIM_FLTINR1_FLT1SRC_0_Pos (2U)
9886#define HRTIM_FLTINR1_FLT1SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_0_Pos)
9887#define HRTIM_FLTINR1_FLT1SRC_0 HRTIM_FLTINR1_FLT1SRC_0_Msk
9888#define HRTIM_FLTINR1_FLT1F_Pos (3U)
9889#define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)
9890#define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk
9891#define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)
9892#define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)
9893#define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)
9894#define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)
9895#define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
9896#define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)
9897#define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk
9898#define HRTIM_FLTINR1_FLT2E_Pos (8U)
9899#define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)
9900#define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk
9901#define HRTIM_FLTINR1_FLT2P_Pos (9U)
9902#define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)
9903#define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk
9904#define HRTIM_FLTINR1_FLT2SRC_0_Pos (10U)
9905#define HRTIM_FLTINR1_FLT2SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_0_Pos)
9906#define HRTIM_FLTINR1_FLT2SRC_0 HRTIM_FLTINR1_FLT2SRC_0_Msk
9907#define HRTIM_FLTINR1_FLT2F_Pos (11U)
9908#define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)
9909#define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk
9910#define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)
9911#define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)
9912#define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)
9913#define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)
9914#define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
9915#define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)
9916#define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk
9917#define HRTIM_FLTINR1_FLT3E_Pos (16U)
9918#define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)
9919#define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk
9920#define HRTIM_FLTINR1_FLT3P_Pos (17U)
9921#define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)
9922#define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk
9923#define HRTIM_FLTINR1_FLT3SRC_0_Pos (18U)
9924#define HRTIM_FLTINR1_FLT3SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_0_Pos)
9925#define HRTIM_FLTINR1_FLT3SRC_0 HRTIM_FLTINR1_FLT3SRC_0_Msk
9926#define HRTIM_FLTINR1_FLT3F_Pos (19U)
9927#define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)
9928#define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk
9929#define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)
9930#define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)
9931#define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)
9932#define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)
9933#define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
9934#define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)
9935#define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk
9936#define HRTIM_FLTINR1_FLT4E_Pos (24U)
9937#define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)
9938#define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk
9939#define HRTIM_FLTINR1_FLT4P_Pos (25U)
9940#define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)
9941#define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk
9942#define HRTIM_FLTINR1_FLT4SRC_0_Pos (26U)
9943#define HRTIM_FLTINR1_FLT4SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_0_Pos)
9944#define HRTIM_FLTINR1_FLT4SRC_0 HRTIM_FLTINR1_FLT4SRC_0_Msk
9945#define HRTIM_FLTINR1_FLT4F_Pos (27U)
9946#define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)
9947#define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk
9948#define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)
9949#define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)
9950#define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)
9951#define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)
9952#define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
9953#define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)
9954#define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk
9956/******************* Bit definition for HRTIM_FLTINR2 register ***************/
9957#define HRTIM_FLTINR2_FLT5E_Pos (0U)
9958#define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)
9959#define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk
9960#define HRTIM_FLTINR2_FLT5P_Pos (1U)
9961#define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)
9962#define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk
9963#define HRTIM_FLTINR2_FLT5SRC_0_Pos (2U)
9964#define HRTIM_FLTINR2_FLT5SRC_0_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_0_Pos)
9965#define HRTIM_FLTINR2_FLT5SRC_0 HRTIM_FLTINR2_FLT5SRC_0_Msk
9966#define HRTIM_FLTINR2_FLT5F_Pos (3U)
9967#define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)
9968#define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk
9969#define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)
9970#define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)
9971#define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)
9972#define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)
9973#define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
9974#define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)
9975#define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk
9976#define HRTIM_FLTINR2_FLT6E_Pos (8U)
9977#define HRTIM_FLTINR2_FLT6E_Msk (0x1UL << HRTIM_FLTINR2_FLT6E_Pos)
9978#define HRTIM_FLTINR2_FLT6E HRTIM_FLTINR2_FLT6E_Msk
9979#define HRTIM_FLTINR2_FLT6P_Pos (9U)
9980#define HRTIM_FLTINR2_FLT6P_Msk (0x1UL << HRTIM_FLTINR2_FLT6P_Pos)
9981#define HRTIM_FLTINR2_FLT6P HRTIM_FLTINR2_FLT6P_Msk
9982#define HRTIM_FLTINR2_FLT6SRC_0_Pos (10U)
9983#define HRTIM_FLTINR2_FLT6SRC_0_Msk (0x1UL << HRTIM_FLTINR2_FLT6SRC_0_Pos)
9984#define HRTIM_FLTINR2_FLT6SRC_0 HRTIM_FLTINR2_FLT6SRC_0_Msk
9985#define HRTIM_FLTINR2_FLT6F_Pos (11U)
9986#define HRTIM_FLTINR2_FLT6F_Msk (0xFUL << HRTIM_FLTINR2_FLT6F_Pos)
9987#define HRTIM_FLTINR2_FLT6F HRTIM_FLTINR2_FLT6F_Msk
9988#define HRTIM_FLTINR2_FLT6F_0 (0x1UL << HRTIM_FLTINR2_FLT6F_Pos)
9989#define HRTIM_FLTINR2_FLT6F_1 (0x2UL << HRTIM_FLTINR2_FLT6F_Pos)
9990#define HRTIM_FLTINR2_FLT6F_2 (0x4UL << HRTIM_FLTINR2_FLT6F_Pos)
9991#define HRTIM_FLTINR2_FLT6F_3 (0x8UL << HRTIM_FLTINR2_FLT6F_Pos)
9992#define HRTIM_FLTINR2_FLT6LCK_Pos (15U)
9993#define HRTIM_FLTINR2_FLT6LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT6LCK_Pos)
9994#define HRTIM_FLTINR2_FLT6LCK HRTIM_FLTINR2_FLT6LCK_Msk
9995#define HRTIM_FLTINR2_FLT1SRC_1_Pos (16U)
9996#define HRTIM_FLTINR2_FLT1SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT1SRC_1_Pos)
9997#define HRTIM_FLTINR2_FLT1SRC_1 HRTIM_FLTINR2_FLT1SRC_1_Msk
9998#define HRTIM_FLTINR2_FLT2SRC_1_Pos (17U)
9999#define HRTIM_FLTINR2_FLT2SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT2SRC_1_Pos)
10000#define HRTIM_FLTINR2_FLT2SRC_1 HRTIM_FLTINR2_FLT2SRC_1_Msk
10001#define HRTIM_FLTINR2_FLT3SRC_1_Pos (18U)
10002#define HRTIM_FLTINR2_FLT3SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT3SRC_1_Pos)
10003#define HRTIM_FLTINR2_FLT3SRC_1 HRTIM_FLTINR2_FLT3SRC_1_Msk
10004#define HRTIM_FLTINR2_FLT4SRC_1_Pos (19U)
10005#define HRTIM_FLTINR2_FLT4SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT4SRC_1_Pos)
10006#define HRTIM_FLTINR2_FLT4SRC_1 HRTIM_FLTINR2_FLT4SRC_1_Msk
10007#define HRTIM_FLTINR2_FLT5SRC_1_Pos (20U)
10008#define HRTIM_FLTINR2_FLT5SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_1_Pos)
10009#define HRTIM_FLTINR2_FLT5SRC_1 HRTIM_FLTINR2_FLT5SRC_1_Msk
10010#define HRTIM_FLTINR2_FLT6SRC_1_Pos (21U)
10011#define HRTIM_FLTINR2_FLT6SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT6SRC_1_Pos)
10012#define HRTIM_FLTINR2_FLT6SRC_1 HRTIM_FLTINR2_FLT6SRC_1_Msk
10013#define HRTIM_FLTINR2_FLTSD_Pos (24U)
10014#define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)
10015#define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk
10016#define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)
10017#define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)
10019/******************* Bit definition for HRTIM_FLTINR3 register ***************/
10020#define HRTIM_FLTINR3_FLT1BLKE_Pos (0U)
10021#define HRTIM_FLTINR3_FLT1BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT1BLKE_Pos)
10022#define HRTIM_FLTINR3_FLT1BLKE HRTIM_FLTINR3_FLT1BLKE_Msk
10023#define HRTIM_FLTINR3_FLT1BLKS_Pos (1U)
10024#define HRTIM_FLTINR3_FLT1BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT1BLKS_Pos)
10025#define HRTIM_FLTINR3_FLT1BLKS HRTIM_FLTINR3_FLT1BLKS_Msk
10026#define HRTIM_FLTINR3_FLT1CNT_Pos (2U)
10027#define HRTIM_FLTINR3_FLT1CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT1CNT_Pos)
10028#define HRTIM_FLTINR3_FLT1CNT HRTIM_FLTINR3_FLT1CNT_Msk
10029#define HRTIM_FLTINR3_FLT1CNT_0 (0x1UL << HRTIM_FLTINR3_FLT1CNT_Pos)
10030#define HRTIM_FLTINR3_FLT1CNT_1 (0x2UL << HRTIM_FLTINR3_FLT1CNT_Pos)
10031#define HRTIM_FLTINR3_FLT1CNT_2 (0x4UL << HRTIM_FLTINR3_FLT1CNT_Pos)
10032#define HRTIM_FLTINR3_FLT1CNT_3 (0x8UL << HRTIM_FLTINR3_FLT1CNT_Pos)
10033#define HRTIM_FLTINR3_FLT1CRES_Pos (6U)
10034#define HRTIM_FLTINR3_FLT1CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT1CRES_Pos)
10035#define HRTIM_FLTINR3_FLT1CRES HRTIM_FLTINR3_FLT1CRES_Msk
10036#define HRTIM_FLTINR3_FLT1RSTM_Pos (7U)
10037#define HRTIM_FLTINR3_FLT1RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT1RSTM_Pos)
10038#define HRTIM_FLTINR3_FLT1RSTM HRTIM_FLTINR3_FLT1RSTM_Msk
10039#define HRTIM_FLTINR3_FLT2BLKE_Pos (8U)
10040#define HRTIM_FLTINR3_FLT2BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT2BLKE_Pos)
10041#define HRTIM_FLTINR3_FLT2BLKE HRTIM_FLTINR3_FLT2BLKE_Msk
10042#define HRTIM_FLTINR3_FLT2BLKS_Pos (9U)
10043#define HRTIM_FLTINR3_FLT2BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT2BLKS_Pos)
10044#define HRTIM_FLTINR3_FLT2BLKS HRTIM_FLTINR3_FLT2BLKS_Msk
10045#define HRTIM_FLTINR3_FLT2CNT_Pos (10U)
10046#define HRTIM_FLTINR3_FLT2CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT2CNT_Pos)
10047#define HRTIM_FLTINR3_FLT2CNT HRTIM_FLTINR3_FLT2CNT_Msk
10048#define HRTIM_FLTINR3_FLT2CNT_0 (0x1UL << HRTIM_FLTINR3_FLT2CNT_Pos)
10049#define HRTIM_FLTINR3_FLT2CNT_1 (0x2UL << HRTIM_FLTINR3_FLT2CNT_Pos)
10050#define HRTIM_FLTINR3_FLT2CNT_2 (0x4UL << HRTIM_FLTINR3_FLT2CNT_Pos)
10051#define HRTIM_FLTINR3_FLT2CNT_3 (0x8UL << HRTIM_FLTINR3_FLT2CNT_Pos)
10052#define HRTIM_FLTINR3_FLT2CRES_Pos (14U)
10053#define HRTIM_FLTINR3_FLT2CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT2CRES_Pos)
10054#define HRTIM_FLTINR3_FLT2CRES HRTIM_FLTINR3_FLT2CRES_Msk
10055#define HRTIM_FLTINR3_FLT2RSTM_Pos (15U)
10056#define HRTIM_FLTINR3_FLT2RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT2RSTM_Pos)
10057#define HRTIM_FLTINR3_FLT2RSTM HRTIM_FLTINR3_FLT2RSTM_Msk
10058#define HRTIM_FLTINR3_FLT3BLKE_Pos (16U)
10059#define HRTIM_FLTINR3_FLT3BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT3BLKE_Pos)
10060#define HRTIM_FLTINR3_FLT3BLKE HRTIM_FLTINR3_FLT3BLKE_Msk
10061#define HRTIM_FLTINR3_FLT3BLKS_Pos (17U)
10062#define HRTIM_FLTINR3_FLT3BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT3BLKS_Pos)
10063#define HRTIM_FLTINR3_FLT3BLKS HRTIM_FLTINR3_FLT3BLKS_Msk
10064#define HRTIM_FLTINR3_FLT3CNT_Pos (18U)
10065#define HRTIM_FLTINR3_FLT3CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT3CNT_Pos)
10066#define HRTIM_FLTINR3_FLT3CNT HRTIM_FLTINR3_FLT3CNT_Msk
10067#define HRTIM_FLTINR3_FLT3CNT_0 (0x1UL << HRTIM_FLTINR3_FLT3CNT_Pos)
10068#define HRTIM_FLTINR3_FLT3CNT_1 (0x2UL << HRTIM_FLTINR3_FLT3CNT_Pos)
10069#define HRTIM_FLTINR3_FLT3CNT_2 (0x4UL << HRTIM_FLTINR3_FLT3CNT_Pos)
10070#define HRTIM_FLTINR3_FLT3CNT_3 (0x8UL << HRTIM_FLTINR3_FLT3CNT_Pos)
10071#define HRTIM_FLTINR3_FLT3CRES_Pos (22U)
10072#define HRTIM_FLTINR3_FLT3CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT3CRES_Pos)
10073#define HRTIM_FLTINR3_FLT3CRES HRTIM_FLTINR3_FLT3CRES_Msk
10074#define HRTIM_FLTINR3_FLT3RSTM_Pos (23U)
10075#define HRTIM_FLTINR3_FLT3RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT3RSTM_Pos)
10076#define HRTIM_FLTINR3_FLT3RSTM HRTIM_FLTINR3_FLT3RSTM_Msk
10077#define HRTIM_FLTINR3_FLT4BLKE_Pos (24U)
10078#define HRTIM_FLTINR3_FLT4BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT4BLKE_Pos)
10079#define HRTIM_FLTINR3_FLT4BLKE HRTIM_FLTINR3_FLT4BLKE_Msk
10080#define HRTIM_FLTINR3_FLT4BLKS_Pos (25U)
10081#define HRTIM_FLTINR3_FLT4BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT4BLKS_Pos)
10082#define HRTIM_FLTINR3_FLT4BLKS HRTIM_FLTINR3_FLT4BLKS_Msk
10083#define HRTIM_FLTINR3_FLT4CNT_Pos (26U)
10084#define HRTIM_FLTINR3_FLT4CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT4CNT_Pos)
10085#define HRTIM_FLTINR3_FLT4CNT HRTIM_FLTINR3_FLT4CNT_Msk
10086#define HRTIM_FLTINR3_FLT4CNT_0 (0x1UL << HRTIM_FLTINR3_FLT4CNT_Pos)
10087#define HRTIM_FLTINR3_FLT4CNT_1 (0x2UL << HRTIM_FLTINR3_FLT4CNT_Pos)
10088#define HRTIM_FLTINR3_FLT4CNT_2 (0x4UL << HRTIM_FLTINR3_FLT4CNT_Pos)
10089#define HRTIM_FLTINR3_FLT4CNT_3 (0x8UL << HRTIM_FLTINR3_FLT4CNT_Pos)
10090#define HRTIM_FLTINR3_FLT4CRES_Pos (30U)
10091#define HRTIM_FLTINR3_FLT4CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT4CRES_Pos)
10092#define HRTIM_FLTINR3_FLT4CRES HRTIM_FLTINR3_FLT4CRES_Msk
10093#define HRTIM_FLTINR3_FLT4RSTM_Pos (31U)
10094#define HRTIM_FLTINR3_FLT4RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT4RSTM_Pos)
10095#define HRTIM_FLTINR3_FLT4RSTM HRTIM_FLTINR3_FLT4RSTM_Msk
10097/******************* Bit definition for HRTIM_FLTINR4 register ***************/
10098#define HRTIM_FLTINR4_FLT5BLKE_Pos (0U)
10099#define HRTIM_FLTINR4_FLT5BLKE_Msk (0x1UL << HRTIM_FLTINR4_FLT5BLKE_Pos)
10100#define HRTIM_FLTINR4_FLT5BLKE HRTIM_FLTINR4_FLT5BLKE_Msk
10101#define HRTIM_FLTINR4_FLT5BLKS_Pos (1U)
10102#define HRTIM_FLTINR4_FLT5BLKS_Msk (0x1UL << HRTIM_FLTINR4_FLT5BLKS_Pos)
10103#define HRTIM_FLTINR4_FLT5BLKS HRTIM_FLTINR4_FLT5BLKS_Msk
10104#define HRTIM_FLTINR4_FLT5CNT_Pos (2U)
10105#define HRTIM_FLTINR4_FLT5CNT_Msk (0xFUL << HRTIM_FLTINR4_FLT5CNT_Pos)
10106#define HRTIM_FLTINR4_FLT5CNT HRTIM_FLTINR4_FLT5CNT_Msk
10107#define HRTIM_FLTINR4_FLT5CNT_0 (0x1UL << HRTIM_FLTINR4_FLT5CNT_Pos)
10108#define HRTIM_FLTINR4_FLT5CNT_1 (0x2UL << HRTIM_FLTINR4_FLT5CNT_Pos)
10109#define HRTIM_FLTINR4_FLT5CNT_2 (0x4UL << HRTIM_FLTINR4_FLT5CNT_Pos)
10110#define HRTIM_FLTINR4_FLT5CNT_3 (0x8UL << HRTIM_FLTINR4_FLT5CNT_Pos)
10111#define HRTIM_FLTINR4_FLT5CRES_Pos (6U)
10112#define HRTIM_FLTINR4_FLT5CRES_Msk (0x1UL << HRTIM_FLTINR4_FLT5CRES_Pos)
10113#define HRTIM_FLTINR4_FLT5CRES HRTIM_FLTINR4_FLT5CRES_Msk
10114#define HRTIM_FLTINR4_FLT5RSTM_Pos (7U)
10115#define HRTIM_FLTINR4_FLT5RSTM_Msk (0x1UL << HRTIM_FLTINR4_FLT5RSTM_Pos)
10116#define HRTIM_FLTINR4_FLT5RSTM HRTIM_FLTINR4_FLT5RSTM_Msk
10117#define HRTIM_FLTINR4_FLT6BLKE_Pos (8U)
10118#define HRTIM_FLTINR4_FLT6BLKE_Msk (0x1UL << HRTIM_FLTINR4_FLT6BLKE_Pos)
10119#define HRTIM_FLTINR4_FLT6BLKE HRTIM_FLTINR4_FLT6BLKE_Msk
10120#define HRTIM_FLTINR4_FLT6BLKS_Pos (9U)
10121#define HRTIM_FLTINR4_FLT6BLKS_Msk (0x1UL << HRTIM_FLTINR4_FLT6BLKS_Pos)
10122#define HRTIM_FLTINR4_FLT6BLKS HRTIM_FLTINR4_FLT6BLKS_Msk
10123#define HRTIM_FLTINR4_FLT6CNT_Pos (10U)
10124#define HRTIM_FLTINR4_FLT6CNT_Msk (0xFUL << HRTIM_FLTINR4_FLT6CNT_Pos)
10125#define HRTIM_FLTINR4_FLT6CNT HRTIM_FLTINR4_FLT6CNT_Msk
10126#define HRTIM_FLTINR4_FLT6CNT_0 (0x1UL << HRTIM_FLTINR4_FLT6CNT_Pos)
10127#define HRTIM_FLTINR4_FLT6CNT_1 (0x2UL << HRTIM_FLTINR4_FLT6CNT_Pos)
10128#define HRTIM_FLTINR4_FLT6CNT_2 (0x4UL << HRTIM_FLTINR4_FLT6CNT_Pos)
10129#define HRTIM_FLTINR4_FLT6CNT_3 (0x8UL << HRTIM_FLTINR4_FLT6CNT_Pos)
10130#define HRTIM_FLTINR4_FLT6CRES_Pos (14U)
10131#define HRTIM_FLTINR4_FLT6CRES_Msk (0x1UL << HRTIM_FLTINR4_FLT6CRES_Pos)
10132#define HRTIM_FLTINR4_FLT6CRES HRTIM_FLTINR4_FLT6CRES_Msk
10133#define HRTIM_FLTINR4_FLT6RSTM_Pos (15U)
10134#define HRTIM_FLTINR4_FLT6RSTM_Msk (0x1UL << HRTIM_FLTINR4_FLT6RSTM_Pos)
10135#define HRTIM_FLTINR4_FLT6RSTM HRTIM_FLTINR4_FLT6RSTM_Msk
10137/******************* Bit definition for HRTIM_BDMUPR register ***************/
10138#define HRTIM_BDMUPR_MCR_Pos (0U)
10139#define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos)
10140#define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk
10141#define HRTIM_BDMUPR_MICR_Pos (1U)
10142#define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos)
10143#define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk
10144#define HRTIM_BDMUPR_MDIER_Pos (2U)
10145#define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos)
10146#define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk
10147#define HRTIM_BDMUPR_MCNT_Pos (3U)
10148#define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos)
10149#define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk
10150#define HRTIM_BDMUPR_MPER_Pos (4U)
10151#define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos)
10152#define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk
10153#define HRTIM_BDMUPR_MREP_Pos (5U)
10154#define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos)
10155#define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk
10156#define HRTIM_BDMUPR_MCMP1_Pos (6U)
10157#define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)
10158#define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk
10159#define HRTIM_BDMUPR_MCMP2_Pos (7U)
10160#define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)
10161#define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk
10162#define HRTIM_BDMUPR_MCMP3_Pos (8U)
10163#define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)
10164#define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk
10165#define HRTIM_BDMUPR_MCMP4_Pos (9U)
10166#define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)
10167#define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk
10169/******************* Bit definition for HRTIM_BDTUPR register ***************/
10170#define HRTIM_BDTUPR_TIMCR_Pos (0U)
10171#define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)
10172#define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk
10173#define HRTIM_BDTUPR_TIMICR_Pos (1U)
10174#define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)
10175#define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk
10176#define HRTIM_BDTUPR_TIMDIER_Pos (2U)
10177#define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)
10178#define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk
10179#define HRTIM_BDTUPR_TIMCNT_Pos (3U)
10180#define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)
10181#define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk
10182#define HRTIM_BDTUPR_TIMPER_Pos (4U)
10183#define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)
10184#define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk
10185#define HRTIM_BDTUPR_TIMREP_Pos (5U)
10186#define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)
10187#define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk
10188#define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
10189#define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)
10190#define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk
10191#define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
10192#define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)
10193#define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk
10194#define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
10195#define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)
10196#define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk
10197#define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
10198#define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)
10199#define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk
10200#define HRTIM_BDTUPR_TIMDTR_Pos (10U)
10201#define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)
10202#define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk
10203#define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
10204#define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)
10205#define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk
10206#define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
10207#define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)
10208#define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk
10209#define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
10210#define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)
10211#define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk
10212#define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
10213#define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)
10214#define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk
10215#define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
10216#define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)
10217#define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk
10218#define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
10219#define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)
10220#define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk
10221#define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
10222#define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)
10223#define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk
10224#define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
10225#define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)
10226#define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk
10227#define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
10228#define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)
10229#define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk
10230#define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
10231#define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)
10232#define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk
10233#define HRTIM_BDTUPR_TIMCR2_Pos (21U)
10234#define HRTIM_BDTUPR_TIMCR2_Msk (0x1UL << HRTIM_BDTUPR_TIMCR2_Pos)
10235#define HRTIM_BDTUPR_TIMCR2 HRTIM_BDTUPR_TIMCR2_Msk
10236#define HRTIM_BDTUPR_TIMEEFR3_Pos (22U)
10237#define HRTIM_BDTUPR_TIMEEFR3_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR3_Pos)
10238#define HRTIM_BDTUPR_TIMEEFR3 HRTIM_BDTUPR_TIMEEFR3_Msk
10240/******************* Bit definition for HRTIM_BDMADR register ***************/
10241#define HRTIM_BDMADR_BDMADR_Pos (0U)
10242#define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)
10243#define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk
10245/******************* Bit definition for HRTIM_ADC Extended Trigger register ***************/
10246#define HRTIM_ADCER_AD5TRG_Pos (0U)
10247#define HRTIM_ADCER_AD5TRG_Msk (0x1FUL << HRTIM_ADCER_AD5TRG_Pos)
10248#define HRTIM_ADCER_AD5TRG HRTIM_ADCER_AD5TRG_Msk
10249#define HRTIM_ADCER_AD6TRG_Pos (5U)
10250#define HRTIM_ADCER_AD6TRG_Msk (0x1FUL << HRTIM_ADCER_AD6TRG_Pos)
10251#define HRTIM_ADCER_AD6TRG HRTIM_ADCER_AD6TRG_Msk
10252#define HRTIM_ADCER_AD7TRG_Pos (10U)
10253#define HRTIM_ADCER_AD7TRG_Msk (0x1FUL << HRTIM_ADCER_AD7TRG_Pos)
10254#define HRTIM_ADCER_AD7TRG HRTIM_ADCER_AD7TRG_Msk
10255#define HRTIM_ADCER_AD8TRG_Pos (16U)
10256#define HRTIM_ADCER_AD8TRG_Msk (0x1FUL << HRTIM_ADCER_AD8TRG_Pos)
10257#define HRTIM_ADCER_AD8TRG HRTIM_ADCER_AD8TRG_Msk
10258#define HRTIM_ADCER_AD9TRG_Pos (21U)
10259#define HRTIM_ADCER_AD9TRG_Msk (0x1FUL << HRTIM_ADCER_AD9TRG_Pos)
10260#define HRTIM_ADCER_AD9TRG HRTIM_ADCER_AD9TRG_Msk
10261#define HRTIM_ADCER_AD10TRG_Pos (26U)
10262#define HRTIM_ADCER_AD10TRG_Msk (0x1FUL << HRTIM_ADCER_AD10TRG_Pos)
10263#define HRTIM_ADCER_AD10TRG HRTIM_ADCER_AD10TRG_Msk
10265/******************* Bit definition for HRTIM_ADC Trigger Update register ***************/
10266#define HRTIM_ADCUR_AD5USRC_Pos (0U)
10267#define HRTIM_ADCUR_AD5USRC_Msk (0x7UL << HRTIM_ADCUR_AD5USRC_Pos)
10268#define HRTIM_ADCUR_AD5USRC HRTIM_ADCUR_AD5USRC_Msk
10269#define HRTIM_ADCUR_AD6USRC_Pos (4U)
10270#define HRTIM_ADCUR_AD6USRC_Msk (0x7UL << HRTIM_ADCUR_AD6USRC_Pos)
10271#define HRTIM_ADCUR_AD6USRC HRTIM_ADCUR_AD6USRC_Msk
10272#define HRTIM_ADCUR_AD7USRC_Pos (8U)
10273#define HRTIM_ADCUR_AD7USRC_Msk (0x7UL << HRTIM_ADCUR_AD7USRC_Pos)
10274#define HRTIM_ADCUR_AD7USRC HRTIM_ADCUR_AD7USRC_Msk
10275#define HRTIM_ADCUR_AD8USRC_Pos (12U)
10276#define HRTIM_ADCUR_AD8USRC_Msk (0x7UL << HRTIM_ADCUR_AD8USRC_Pos)
10277#define HRTIM_ADCUR_AD8USRC HRTIM_ADCUR_AD8USRC_Msk
10278#define HRTIM_ADCUR_AD9USRC_Pos (16U)
10279#define HRTIM_ADCUR_AD9USRC_Msk (0x7UL << HRTIM_ADCUR_AD9USRC_Pos)
10280#define HRTIM_ADCUR_AD9USRC HRTIM_ADCUR_AD9USRC_Msk
10281#define HRTIM_ADCUR_AD10USRC_Pos (20U)
10282#define HRTIM_ADCUR_AD10USRC_Msk (0x7UL << HRTIM_ADCUR_AD10USRC_Pos)
10283#define HRTIM_ADCUR_AD10USRC HRTIM_ADCUR_AD10USRC_Msk
10285/******************* Bit definition for HRTIM_ADCPS1 ADC Post Scaler register 1 ***************/
10286#define HRTIM_ADCPS1_AD1PSC_Pos (0U)
10287#define HRTIM_ADCPS1_AD1PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD1PSC_Pos)
10288#define HRTIM_ADCPS1_AD1PSC HRTIM_ADCPS1_AD1PSC_Msk
10289#define HRTIM_ADCPS1_AD2PSC_Pos (6U)
10290#define HRTIM_ADCPS1_AD2PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD2PSC_Pos)
10291#define HRTIM_ADCPS1_AD2PSC HRTIM_ADCPS1_AD2PSC_Msk
10292#define HRTIM_ADCPS1_AD3PSC_Pos (12U)
10293#define HRTIM_ADCPS1_AD3PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD3PSC_Pos)
10294#define HRTIM_ADCPS1_AD3PSC HRTIM_ADCPS1_AD3PSC_Msk
10295#define HRTIM_ADCPS1_AD4PSC_Pos (18U)
10296#define HRTIM_ADCPS1_AD4PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD4PSC_Pos)
10297#define HRTIM_ADCPS1_AD4PSC HRTIM_ADCPS1_AD4PSC_Msk
10298#define HRTIM_ADCPS1_AD5PSC_Pos (24U)
10299#define HRTIM_ADCPS1_AD5PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD5PSC_Pos)
10300#define HRTIM_ADCPS1_AD5PSC HRTIM_ADCPS1_AD5PSC_Msk
10302/******************* Bit definition for HRTIM_ADCPS2 ADC Post Scaler register 2 ***************/
10303#define HRTIM_ADCPS2_AD6PSC_Pos (0U)
10304#define HRTIM_ADCPS2_AD6PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD6PSC_Pos)
10305#define HRTIM_ADCPS2_AD6PSC HRTIM_ADCPS2_AD6PSC_Msk
10306#define HRTIM_ADCPS2_AD7PSC_Pos (6U)
10307#define HRTIM_ADCPS2_AD7PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD7PSC_Pos)
10308#define HRTIM_ADCPS2_AD7PSC HRTIM_ADCPS2_AD7PSC_Msk
10309#define HRTIM_ADCPS2_AD8PSC_Pos (12U)
10310#define HRTIM_ADCPS2_AD8PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD8PSC_Pos)
10311#define HRTIM_ADCPS2_AD8PSC HRTIM_ADCPS2_AD8PSC_Msk
10312#define HRTIM_ADCPS2_AD9PSC_Pos (18U)
10313#define HRTIM_ADCPS2_AD9PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD9PSC_Pos)
10314#define HRTIM_ADCPS2_AD9PSC HRTIM_ADCPS2_AD9PSC_Msk
10315#define HRTIM_ADCPS2_AD10PSC_Pos (24U)
10316#define HRTIM_ADCPS2_AD10PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD10PSC_Pos)
10317#define HRTIM_ADCPS2_AD10PSC HRTIM_ADCPS2_AD10PSC_Msk
10320/******************************************************************************/
10321/* */
10322/* Inter-integrated Circuit Interface (I2C) */
10323/* */
10324/******************************************************************************/
10325/******************* Bit definition for I2C_CR1 register *******************/
10326#define I2C_CR1_PE_Pos (0U)
10327#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
10328#define I2C_CR1_PE I2C_CR1_PE_Msk
10329#define I2C_CR1_TXIE_Pos (1U)
10330#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
10331#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
10332#define I2C_CR1_RXIE_Pos (2U)
10333#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
10334#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
10335#define I2C_CR1_ADDRIE_Pos (3U)
10336#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
10337#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
10338#define I2C_CR1_NACKIE_Pos (4U)
10339#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
10340#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
10341#define I2C_CR1_STOPIE_Pos (5U)
10342#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
10343#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
10344#define I2C_CR1_TCIE_Pos (6U)
10345#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
10346#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
10347#define I2C_CR1_ERRIE_Pos (7U)
10348#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
10349#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
10350#define I2C_CR1_DNF_Pos (8U)
10351#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
10352#define I2C_CR1_DNF I2C_CR1_DNF_Msk
10353#define I2C_CR1_ANFOFF_Pos (12U)
10354#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
10355#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
10356#define I2C_CR1_SWRST_Pos (13U)
10357#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
10358#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
10359#define I2C_CR1_TXDMAEN_Pos (14U)
10360#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
10361#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
10362#define I2C_CR1_RXDMAEN_Pos (15U)
10363#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
10364#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
10365#define I2C_CR1_SBC_Pos (16U)
10366#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
10367#define I2C_CR1_SBC I2C_CR1_SBC_Msk
10368#define I2C_CR1_NOSTRETCH_Pos (17U)
10369#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
10370#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
10371#define I2C_CR1_WUPEN_Pos (18U)
10372#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
10373#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
10374#define I2C_CR1_GCEN_Pos (19U)
10375#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
10376#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
10377#define I2C_CR1_SMBHEN_Pos (20U)
10378#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
10379#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
10380#define I2C_CR1_SMBDEN_Pos (21U)
10381#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
10382#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
10383#define I2C_CR1_ALERTEN_Pos (22U)
10384#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
10385#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
10386#define I2C_CR1_PECEN_Pos (23U)
10387#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
10388#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
10390/****************** Bit definition for I2C_CR2 register ********************/
10391#define I2C_CR2_SADD_Pos (0U)
10392#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
10393#define I2C_CR2_SADD I2C_CR2_SADD_Msk
10394#define I2C_CR2_RD_WRN_Pos (10U)
10395#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
10396#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
10397#define I2C_CR2_ADD10_Pos (11U)
10398#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
10399#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
10400#define I2C_CR2_HEAD10R_Pos (12U)
10401#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
10402#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
10403#define I2C_CR2_START_Pos (13U)
10404#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
10405#define I2C_CR2_START I2C_CR2_START_Msk
10406#define I2C_CR2_STOP_Pos (14U)
10407#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
10408#define I2C_CR2_STOP I2C_CR2_STOP_Msk
10409#define I2C_CR2_NACK_Pos (15U)
10410#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
10411#define I2C_CR2_NACK I2C_CR2_NACK_Msk
10412#define I2C_CR2_NBYTES_Pos (16U)
10413#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
10414#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
10415#define I2C_CR2_RELOAD_Pos (24U)
10416#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
10417#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
10418#define I2C_CR2_AUTOEND_Pos (25U)
10419#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
10420#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
10421#define I2C_CR2_PECBYTE_Pos (26U)
10422#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
10423#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
10425/******************* Bit definition for I2C_OAR1 register ******************/
10426#define I2C_OAR1_OA1_Pos (0U)
10427#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
10428#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
10429#define I2C_OAR1_OA1MODE_Pos (10U)
10430#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
10431#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
10432#define I2C_OAR1_OA1EN_Pos (15U)
10433#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
10434#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
10436/******************* Bit definition for I2C_OAR2 register ******************/
10437#define I2C_OAR2_OA2_Pos (1U)
10438#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
10439#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
10440#define I2C_OAR2_OA2MSK_Pos (8U)
10441#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
10442#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
10443#define I2C_OAR2_OA2NOMASK (0x00000000U)
10444#define I2C_OAR2_OA2MASK01_Pos (8U)
10445#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
10446#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
10447#define I2C_OAR2_OA2MASK02_Pos (9U)
10448#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
10449#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
10450#define I2C_OAR2_OA2MASK03_Pos (8U)
10451#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
10452#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
10453#define I2C_OAR2_OA2MASK04_Pos (10U)
10454#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
10455#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
10456#define I2C_OAR2_OA2MASK05_Pos (8U)
10457#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
10458#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
10459#define I2C_OAR2_OA2MASK06_Pos (9U)
10460#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
10461#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
10462#define I2C_OAR2_OA2MASK07_Pos (8U)
10463#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
10464#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
10465#define I2C_OAR2_OA2EN_Pos (15U)
10466#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
10467#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
10469/******************* Bit definition for I2C_TIMINGR register *******************/
10470#define I2C_TIMINGR_SCLL_Pos (0U)
10471#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
10472#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
10473#define I2C_TIMINGR_SCLH_Pos (8U)
10474#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
10475#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
10476#define I2C_TIMINGR_SDADEL_Pos (16U)
10477#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
10478#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
10479#define I2C_TIMINGR_SCLDEL_Pos (20U)
10480#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
10481#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
10482#define I2C_TIMINGR_PRESC_Pos (28U)
10483#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
10484#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
10486/******************* Bit definition for I2C_TIMEOUTR register *******************/
10487#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
10488#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
10489#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
10490#define I2C_TIMEOUTR_TIDLE_Pos (12U)
10491#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
10492#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
10493#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
10494#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
10495#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
10496#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
10497#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
10498#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
10499#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
10500#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
10501#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
10503/****************** Bit definition for I2C_ISR register *********************/
10504#define I2C_ISR_TXE_Pos (0U)
10505#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
10506#define I2C_ISR_TXE I2C_ISR_TXE_Msk
10507#define I2C_ISR_TXIS_Pos (1U)
10508#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
10509#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
10510#define I2C_ISR_RXNE_Pos (2U)
10511#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
10512#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
10513#define I2C_ISR_ADDR_Pos (3U)
10514#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
10515#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
10516#define I2C_ISR_NACKF_Pos (4U)
10517#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
10518#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
10519#define I2C_ISR_STOPF_Pos (5U)
10520#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
10521#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
10522#define I2C_ISR_TC_Pos (6U)
10523#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
10524#define I2C_ISR_TC I2C_ISR_TC_Msk
10525#define I2C_ISR_TCR_Pos (7U)
10526#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
10527#define I2C_ISR_TCR I2C_ISR_TCR_Msk
10528#define I2C_ISR_BERR_Pos (8U)
10529#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
10530#define I2C_ISR_BERR I2C_ISR_BERR_Msk
10531#define I2C_ISR_ARLO_Pos (9U)
10532#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
10533#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
10534#define I2C_ISR_OVR_Pos (10U)
10535#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
10536#define I2C_ISR_OVR I2C_ISR_OVR_Msk
10537#define I2C_ISR_PECERR_Pos (11U)
10538#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
10539#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
10540#define I2C_ISR_TIMEOUT_Pos (12U)
10541#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
10542#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
10543#define I2C_ISR_ALERT_Pos (13U)
10544#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
10545#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
10546#define I2C_ISR_BUSY_Pos (15U)
10547#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
10548#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
10549#define I2C_ISR_DIR_Pos (16U)
10550#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
10551#define I2C_ISR_DIR I2C_ISR_DIR_Msk
10552#define I2C_ISR_ADDCODE_Pos (17U)
10553#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
10554#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
10556/****************** Bit definition for I2C_ICR register *********************/
10557#define I2C_ICR_ADDRCF_Pos (3U)
10558#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
10559#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
10560#define I2C_ICR_NACKCF_Pos (4U)
10561#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
10562#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
10563#define I2C_ICR_STOPCF_Pos (5U)
10564#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
10565#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
10566#define I2C_ICR_BERRCF_Pos (8U)
10567#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
10568#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
10569#define I2C_ICR_ARLOCF_Pos (9U)
10570#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
10571#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
10572#define I2C_ICR_OVRCF_Pos (10U)
10573#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
10574#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
10575#define I2C_ICR_PECCF_Pos (11U)
10576#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
10577#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
10578#define I2C_ICR_TIMOUTCF_Pos (12U)
10579#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
10580#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
10581#define I2C_ICR_ALERTCF_Pos (13U)
10582#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
10583#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
10585/****************** Bit definition for I2C_PECR register *********************/
10586#define I2C_PECR_PEC_Pos (0U)
10587#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
10588#define I2C_PECR_PEC I2C_PECR_PEC_Msk
10590/****************** Bit definition for I2C_RXDR register *********************/
10591#define I2C_RXDR_RXDATA_Pos (0U)
10592#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
10593#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
10595/****************** Bit definition for I2C_TXDR register *********************/
10596#define I2C_TXDR_TXDATA_Pos (0U)
10597#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
10598#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
10600/******************************************************************************/
10601/* */
10602/* Independent WATCHDOG */
10603/* */
10604/******************************************************************************/
10605/******************* Bit definition for IWDG_KR register ********************/
10606#define IWDG_KR_KEY_Pos (0U)
10607#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
10608#define IWDG_KR_KEY IWDG_KR_KEY_Msk
10610/******************* Bit definition for IWDG_PR register ********************/
10611#define IWDG_PR_PR_Pos (0U)
10612#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
10613#define IWDG_PR_PR IWDG_PR_PR_Msk
10614#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
10615#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
10616#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
10618/******************* Bit definition for IWDG_RLR register *******************/
10619#define IWDG_RLR_RL_Pos (0U)
10620#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
10621#define IWDG_RLR_RL IWDG_RLR_RL_Msk
10623/******************* Bit definition for IWDG_SR register ********************/
10624#define IWDG_SR_PVU_Pos (0U)
10625#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
10626#define IWDG_SR_PVU IWDG_SR_PVU_Msk
10627#define IWDG_SR_RVU_Pos (1U)
10628#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
10629#define IWDG_SR_RVU IWDG_SR_RVU_Msk
10630#define IWDG_SR_WVU_Pos (2U)
10631#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
10632#define IWDG_SR_WVU IWDG_SR_WVU_Msk
10634/******************* Bit definition for IWDG_KR register ********************/
10635#define IWDG_WINR_WIN_Pos (0U)
10636#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
10637#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
10639/******************************************************************************/
10640/* */
10641/* Operational Amplifier (OPAMP) */
10642/* */
10643/******************************************************************************/
10644/********************* Bit definition for OPAMPx_CSR register ***************/
10645#define OPAMP_CSR_OPAMPxEN_Pos (0U)
10646#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
10647#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
10648#define OPAMP_CSR_FORCEVP_Pos (1U)
10649#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)
10650#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk
10651#define OPAMP_CSR_VPSEL_Pos (2U)
10652#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)
10653#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
10654#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)
10655#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)
10656#define OPAMP_CSR_USERTRIM_Pos (4U)
10657#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
10658#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
10659#define OPAMP_CSR_VMSEL_Pos (5U)
10660#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
10661#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
10662#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
10663#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
10664#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
10665#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos)
10666#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk
10667#define OPAMP_CSR_OPAMPINTEN_Pos (8U)
10668#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos)
10669#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk
10670#define OPAMP_CSR_CALON_Pos (11U)
10671#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
10672#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
10673#define OPAMP_CSR_CALSEL_Pos (12U)
10674#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)
10675#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
10676#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)
10677#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)
10678#define OPAMP_CSR_PGGAIN_Pos (14U)
10679#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos)
10680#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
10681#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
10682#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
10683#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)
10684#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)
10685#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos)
10686#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
10687#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)
10688#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk
10689#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
10690#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)
10691#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk
10692#define OPAMP_CSR_OUTCAL_Pos (30U)
10693#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos)
10694#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk
10695#define OPAMP_CSR_LOCK_Pos (31U)
10696#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos)
10697#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk
10699/********************* Bit definition for OPAMPx_TCMR register ***************/
10700
10701#define OPAMP_TCMR_VMSSEL_Pos (0U)
10702#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos)
10703#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk
10704#define OPAMP_TCMR_VPSSEL_Pos (1U)
10705#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos)
10706#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk
10707#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos)
10708#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos)
10709#define OPAMP_TCMR_T1CMEN_Pos (3U)
10710#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos)
10711#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk
10712#define OPAMP_TCMR_T8CMEN_Pos (4U)
10713#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos)
10714#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk
10715#define OPAMP_TCMR_T20CMEN_Pos (5U)
10716#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos)
10717#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk
10718#define OPAMP_TCMR_LOCK_Pos (31U)
10719#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos)
10720#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk
10723/******************************************************************************/
10724/* */
10725/* Power Control */
10726/* */
10727/******************************************************************************/
10728
10729/******************** Bit definition for PWR_CR1 register ********************/
10730
10731#define PWR_CR1_LPR_Pos (14U)
10732#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)
10733#define PWR_CR1_LPR PWR_CR1_LPR_Msk
10734#define PWR_CR1_VOS_Pos (9U)
10735#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
10736#define PWR_CR1_VOS PWR_CR1_VOS_Msk
10737#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
10738#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
10739#define PWR_CR1_DBP_Pos (8U)
10740#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
10741#define PWR_CR1_DBP PWR_CR1_DBP_Msk
10742#define PWR_CR1_LPMS_Pos (0U)
10743#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)
10744#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk
10745#define PWR_CR1_LPMS_STOP0 (0x00000000U)
10746#define PWR_CR1_LPMS_STOP1_Pos (0U)
10747#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos)
10748#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk
10749#define PWR_CR1_LPMS_STANDBY_Pos (0U)
10750#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)
10751#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk
10752#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
10753#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)
10754#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk
10757/******************** Bit definition for PWR_CR2 register ********************/
10758
10760#define PWR_CR2_PVME_Pos (4U)
10761#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos)
10762#define PWR_CR2_PVME PWR_CR2_PVME_Msk
10763#define PWR_CR2_PVME4_Pos (7U)
10764#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos)
10765#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk
10766#define PWR_CR2_PVME3_Pos (6U)
10767#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos)
10768#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk
10769#define PWR_CR2_PVME2_Pos (5U)
10770#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos)
10771#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk
10772#define PWR_CR2_PVME1_Pos (4U)
10773#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos)
10774#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk
10777#define PWR_CR2_PLS_Pos (1U)
10778#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos)
10779#define PWR_CR2_PLS PWR_CR2_PLS_Msk
10780#define PWR_CR2_PLS_LEV0 (0x00000000U)
10781#define PWR_CR2_PLS_LEV1_Pos (1U)
10782#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos)
10783#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk
10784#define PWR_CR2_PLS_LEV2_Pos (2U)
10785#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos)
10786#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk
10787#define PWR_CR2_PLS_LEV3_Pos (1U)
10788#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos)
10789#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk
10790#define PWR_CR2_PLS_LEV4_Pos (3U)
10791#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos)
10792#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk
10793#define PWR_CR2_PLS_LEV5_Pos (1U)
10794#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos)
10795#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk
10796#define PWR_CR2_PLS_LEV6_Pos (2U)
10797#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos)
10798#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk
10799#define PWR_CR2_PLS_LEV7_Pos (1U)
10800#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos)
10801#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk
10802#define PWR_CR2_PVDE_Pos (0U)
10803#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos)
10804#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk
10806/******************** Bit definition for PWR_CR3 register ********************/
10807#define PWR_CR3_EIWF_Pos (15U)
10808#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos)
10809#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk
10810#define PWR_CR3_UCPD_DBDIS_Pos (14U)
10811#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos)
10812#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk
10813#define PWR_CR3_UCPD_STDBY_Pos (13U)
10814#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos)
10815#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk
10816#define PWR_CR3_APC_Pos (10U)
10817#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)
10818#define PWR_CR3_APC PWR_CR3_APC_Msk
10819#define PWR_CR3_RRS_Pos (8U)
10820#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos)
10821#define PWR_CR3_RRS PWR_CR3_RRS_Msk
10822#define PWR_CR3_EWUP5_Pos (4U)
10823#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos)
10824#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk
10825#define PWR_CR3_EWUP4_Pos (3U)
10826#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)
10827#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk
10828#define PWR_CR3_EWUP3_Pos (2U)
10829#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos)
10830#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk
10831#define PWR_CR3_EWUP2_Pos (1U)
10832#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)
10833#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk
10834#define PWR_CR3_EWUP1_Pos (0U)
10835#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)
10836#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk
10837#define PWR_CR3_EWUP_Pos (0U)
10838#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos)
10839#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk
10841/******************** Bit definition for PWR_CR4 register ********************/
10842#define PWR_CR4_VBRS_Pos (9U)
10843#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)
10844#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk
10845#define PWR_CR4_VBE_Pos (8U)
10846#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)
10847#define PWR_CR4_VBE PWR_CR4_VBE_Msk
10848#define PWR_CR4_WP5_Pos (4U)
10849#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos)
10850#define PWR_CR4_WP5 PWR_CR4_WP5_Msk
10851#define PWR_CR4_WP4_Pos (3U)
10852#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)
10853#define PWR_CR4_WP4 PWR_CR4_WP4_Msk
10854#define PWR_CR4_WP3_Pos (2U)
10855#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos)
10856#define PWR_CR4_WP3 PWR_CR4_WP3_Msk
10857#define PWR_CR4_WP2_Pos (1U)
10858#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)
10859#define PWR_CR4_WP2 PWR_CR4_WP2_Msk
10860#define PWR_CR4_WP1_Pos (0U)
10861#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)
10862#define PWR_CR4_WP1 PWR_CR4_WP1_Msk
10864/******************** Bit definition for PWR_SR1 register ********************/
10865#define PWR_SR1_WUFI_Pos (15U)
10866#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)
10867#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk
10868#define PWR_SR1_SBF_Pos (8U)
10869#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)
10870#define PWR_SR1_SBF PWR_SR1_SBF_Msk
10871#define PWR_SR1_WUF_Pos (0U)
10872#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos)
10873#define PWR_SR1_WUF PWR_SR1_WUF_Msk
10874#define PWR_SR1_WUF5_Pos (4U)
10875#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos)
10876#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk
10877#define PWR_SR1_WUF4_Pos (3U)
10878#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)
10879#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk
10880#define PWR_SR1_WUF3_Pos (2U)
10881#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos)
10882#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk
10883#define PWR_SR1_WUF2_Pos (1U)
10884#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)
10885#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk
10886#define PWR_SR1_WUF1_Pos (0U)
10887#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)
10888#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk
10890/******************** Bit definition for PWR_SR2 register ********************/
10891#define PWR_SR2_PVMO4_Pos (15U)
10892#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos)
10893#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk
10894#define PWR_SR2_PVMO3_Pos (14U)
10895#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos)
10896#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk
10897#define PWR_SR2_PVMO2_Pos (13U)
10898#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos)
10899#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk
10900#define PWR_SR2_PVMO1_Pos (12U)
10901#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos)
10902#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk
10903#define PWR_SR2_PVDO_Pos (11U)
10904#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos)
10905#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk
10906#define PWR_SR2_VOSF_Pos (10U)
10907#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)
10908#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk
10909#define PWR_SR2_REGLPF_Pos (9U)
10910#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)
10911#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk
10912#define PWR_SR2_REGLPS_Pos (8U)
10913#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)
10914#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk
10916/******************** Bit definition for PWR_SCR register ********************/
10917#define PWR_SCR_CSBF_Pos (8U)
10918#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)
10919#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk
10920#define PWR_SCR_CWUF_Pos (0U)
10921#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos)
10922#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk
10923#define PWR_SCR_CWUF5_Pos (4U)
10924#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos)
10925#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk
10926#define PWR_SCR_CWUF4_Pos (3U)
10927#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)
10928#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk
10929#define PWR_SCR_CWUF3_Pos (2U)
10930#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos)
10931#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk
10932#define PWR_SCR_CWUF2_Pos (1U)
10933#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)
10934#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk
10935#define PWR_SCR_CWUF1_Pos (0U)
10936#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)
10937#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk
10939/******************** Bit definition for PWR_PUCRA register ********************/
10940#define PWR_PUCRA_PA15_Pos (15U)
10941#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos)
10942#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk
10943#define PWR_PUCRA_PA13_Pos (13U)
10944#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos)
10945#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk
10946#define PWR_PUCRA_PA12_Pos (12U)
10947#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos)
10948#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk
10949#define PWR_PUCRA_PA11_Pos (11U)
10950#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos)
10951#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk
10952#define PWR_PUCRA_PA10_Pos (10U)
10953#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos)
10954#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk
10955#define PWR_PUCRA_PA9_Pos (9U)
10956#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos)
10957#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk
10958#define PWR_PUCRA_PA8_Pos (8U)
10959#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos)
10960#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk
10961#define PWR_PUCRA_PA7_Pos (7U)
10962#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos)
10963#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk
10964#define PWR_PUCRA_PA6_Pos (6U)
10965#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos)
10966#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk
10967#define PWR_PUCRA_PA5_Pos (5U)
10968#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos)
10969#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk
10970#define PWR_PUCRA_PA4_Pos (4U)
10971#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos)
10972#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk
10973#define PWR_PUCRA_PA3_Pos (3U)
10974#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos)
10975#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk
10976#define PWR_PUCRA_PA2_Pos (2U)
10977#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos)
10978#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk
10979#define PWR_PUCRA_PA1_Pos (1U)
10980#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos)
10981#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk
10982#define PWR_PUCRA_PA0_Pos (0U)
10983#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos)
10984#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk
10986/******************** Bit definition for PWR_PDCRA register ********************/
10987#define PWR_PDCRA_PA14_Pos (14U)
10988#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos)
10989#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk
10990#define PWR_PDCRA_PA12_Pos (12U)
10991#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos)
10992#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk
10993#define PWR_PDCRA_PA11_Pos (11U)
10994#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos)
10995#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk
10996#define PWR_PDCRA_PA10_Pos (10U)
10997#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos)
10998#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk
10999#define PWR_PDCRA_PA9_Pos (9U)
11000#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos)
11001#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk
11002#define PWR_PDCRA_PA8_Pos (8U)
11003#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos)
11004#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk
11005#define PWR_PDCRA_PA7_Pos (7U)
11006#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos)
11007#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk
11008#define PWR_PDCRA_PA6_Pos (6U)
11009#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos)
11010#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk
11011#define PWR_PDCRA_PA5_Pos (5U)
11012#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos)
11013#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk
11014#define PWR_PDCRA_PA4_Pos (4U)
11015#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos)
11016#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk
11017#define PWR_PDCRA_PA3_Pos (3U)
11018#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos)
11019#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk
11020#define PWR_PDCRA_PA2_Pos (2U)
11021#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos)
11022#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk
11023#define PWR_PDCRA_PA1_Pos (1U)
11024#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos)
11025#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk
11026#define PWR_PDCRA_PA0_Pos (0U)
11027#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos)
11028#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk
11030/******************** Bit definition for PWR_PUCRB register ********************/
11031
11032#define PWR_PUCRB_PB15_Pos (15U)
11033#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos)
11034#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk
11035#define PWR_PUCRB_PB14_Pos (14U)
11036#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos)
11037#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk
11038#define PWR_PUCRB_PB13_Pos (13U)
11039#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos)
11040#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk
11041#define PWR_PUCRB_PB12_Pos (12U)
11042#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos)
11043#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk
11044#define PWR_PUCRB_PB11_Pos (11U)
11045#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos)
11046#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk
11047#define PWR_PUCRB_PB10_Pos (10U)
11048#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos)
11049#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk
11050#define PWR_PUCRB_PB9_Pos (9U)
11051#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos)
11052#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk
11053#define PWR_PUCRB_PB8_Pos (8U)
11054#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos)
11055#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk
11056#define PWR_PUCRB_PB7_Pos (7U)
11057#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos)
11058#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk
11059#define PWR_PUCRB_PB6_Pos (6U)
11060#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos)
11061#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk
11062#define PWR_PUCRB_PB5_Pos (5U)
11063#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos)
11064#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk
11065#define PWR_PUCRB_PB4_Pos (4U)
11066#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos)
11067#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk
11068#define PWR_PUCRB_PB3_Pos (3U)
11069#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos)
11070#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk
11071#define PWR_PUCRB_PB2_Pos (2U)
11072#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos)
11073#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk
11074#define PWR_PUCRB_PB1_Pos (1U)
11075#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos)
11076#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk
11077#define PWR_PUCRB_PB0_Pos (0U)
11078#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos)
11079#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk
11081/******************** Bit definition for PWR_PDCRB register ********************/
11082#define PWR_PDCRB_PB15_Pos (15U)
11083#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos)
11084#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk
11085#define PWR_PDCRB_PB14_Pos (14U)
11086#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos)
11087#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk
11088#define PWR_PDCRB_PB13_Pos (13U)
11089#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos)
11090#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk
11091#define PWR_PDCRB_PB12_Pos (12U)
11092#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos)
11093#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk
11094#define PWR_PDCRB_PB11_Pos (11U)
11095#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos)
11096#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk
11097#define PWR_PDCRB_PB10_Pos (10U)
11098#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos)
11099#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk
11100#define PWR_PDCRB_PB9_Pos (9U)
11101#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos)
11102#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk
11103#define PWR_PDCRB_PB8_Pos (8U)
11104#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos)
11105#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk
11106#define PWR_PDCRB_PB7_Pos (7U)
11107#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos)
11108#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk
11109#define PWR_PDCRB_PB6_Pos (6U)
11110#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos)
11111#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk
11112#define PWR_PDCRB_PB5_Pos (5U)
11113#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos)
11114#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk
11115#define PWR_PDCRB_PB3_Pos (3U)
11116#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos)
11117#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk
11118#define PWR_PDCRB_PB2_Pos (2U)
11119#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos)
11120#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk
11121#define PWR_PDCRB_PB1_Pos (1U)
11122#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos)
11123#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk
11124#define PWR_PDCRB_PB0_Pos (0U)
11125#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos)
11126#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk
11128/******************** Bit definition for PWR_PUCRC register ********************/
11129#define PWR_PUCRC_PC15_Pos (15U)
11130#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos)
11131#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk
11132#define PWR_PUCRC_PC14_Pos (14U)
11133#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos)
11134#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk
11135#define PWR_PUCRC_PC13_Pos (13U)
11136#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos)
11137#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk
11138#define PWR_PUCRC_PC12_Pos (12U)
11139#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos)
11140#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk
11141#define PWR_PUCRC_PC11_Pos (11U)
11142#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos)
11143#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk
11144#define PWR_PUCRC_PC10_Pos (10U)
11145#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos)
11146#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk
11147#define PWR_PUCRC_PC9_Pos (9U)
11148#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos)
11149#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk
11150#define PWR_PUCRC_PC8_Pos (8U)
11151#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos)
11152#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk
11153#define PWR_PUCRC_PC7_Pos (7U)
11154#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos)
11155#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk
11156#define PWR_PUCRC_PC6_Pos (6U)
11157#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos)
11158#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk
11159#define PWR_PUCRC_PC5_Pos (5U)
11160#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos)
11161#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk
11162#define PWR_PUCRC_PC4_Pos (4U)
11163#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos)
11164#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk
11165#define PWR_PUCRC_PC3_Pos (3U)
11166#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos)
11167#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk
11168#define PWR_PUCRC_PC2_Pos (2U)
11169#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos)
11170#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk
11171#define PWR_PUCRC_PC1_Pos (1U)
11172#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos)
11173#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk
11174#define PWR_PUCRC_PC0_Pos (0U)
11175#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos)
11176#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk
11178/******************** Bit definition for PWR_PDCRC register ********************/
11179#define PWR_PDCRC_PC15_Pos (15U)
11180#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos)
11181#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk
11182#define PWR_PDCRC_PC14_Pos (14U)
11183#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos)
11184#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk
11185#define PWR_PDCRC_PC13_Pos (13U)
11186#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos)
11187#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk
11188#define PWR_PDCRC_PC12_Pos (12U)
11189#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos)
11190#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk
11191#define PWR_PDCRC_PC11_Pos (11U)
11192#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos)
11193#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk
11194#define PWR_PDCRC_PC10_Pos (10U)
11195#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos)
11196#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk
11197#define PWR_PDCRC_PC9_Pos (9U)
11198#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos)
11199#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk
11200#define PWR_PDCRC_PC8_Pos (8U)
11201#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos)
11202#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk
11203#define PWR_PDCRC_PC7_Pos (7U)
11204#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos)
11205#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk
11206#define PWR_PDCRC_PC6_Pos (6U)
11207#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos)
11208#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk
11209#define PWR_PDCRC_PC5_Pos (5U)
11210#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos)
11211#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk
11212#define PWR_PDCRC_PC4_Pos (4U)
11213#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos)
11214#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk
11215#define PWR_PDCRC_PC3_Pos (3U)
11216#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos)
11217#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk
11218#define PWR_PDCRC_PC2_Pos (2U)
11219#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos)
11220#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk
11221#define PWR_PDCRC_PC1_Pos (1U)
11222#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos)
11223#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk
11224#define PWR_PDCRC_PC0_Pos (0U)
11225#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos)
11226#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk
11228/******************** Bit definition for PWR_PUCRD register ********************/
11229#define PWR_PUCRD_PD15_Pos (15U)
11230#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos)
11231#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk
11232#define PWR_PUCRD_PD14_Pos (14U)
11233#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos)
11234#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk
11235#define PWR_PUCRD_PD13_Pos (13U)
11236#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos)
11237#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk
11238#define PWR_PUCRD_PD12_Pos (12U)
11239#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos)
11240#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk
11241#define PWR_PUCRD_PD11_Pos (11U)
11242#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos)
11243#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk
11244#define PWR_PUCRD_PD10_Pos (10U)
11245#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos)
11246#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk
11247#define PWR_PUCRD_PD9_Pos (9U)
11248#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos)
11249#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk
11250#define PWR_PUCRD_PD8_Pos (8U)
11251#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos)
11252#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk
11253#define PWR_PUCRD_PD7_Pos (7U)
11254#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos)
11255#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk
11256#define PWR_PUCRD_PD6_Pos (6U)
11257#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos)
11258#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk
11259#define PWR_PUCRD_PD5_Pos (5U)
11260#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos)
11261#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk
11262#define PWR_PUCRD_PD4_Pos (4U)
11263#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos)
11264#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk
11265#define PWR_PUCRD_PD3_Pos (3U)
11266#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos)
11267#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk
11268#define PWR_PUCRD_PD2_Pos (2U)
11269#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos)
11270#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk
11271#define PWR_PUCRD_PD1_Pos (1U)
11272#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos)
11273#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk
11274#define PWR_PUCRD_PD0_Pos (0U)
11275#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos)
11276#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk
11278/******************** Bit definition for PWR_PDCRD register ********************/
11279#define PWR_PDCRD_PD15_Pos (15U)
11280#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos)
11281#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk
11282#define PWR_PDCRD_PD14_Pos (14U)
11283#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos)
11284#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk
11285#define PWR_PDCRD_PD13_Pos (13U)
11286#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos)
11287#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk
11288#define PWR_PDCRD_PD12_Pos (12U)
11289#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos)
11290#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk
11291#define PWR_PDCRD_PD11_Pos (11U)
11292#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos)
11293#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk
11294#define PWR_PDCRD_PD10_Pos (10U)
11295#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos)
11296#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk
11297#define PWR_PDCRD_PD9_Pos (9U)
11298#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos)
11299#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk
11300#define PWR_PDCRD_PD8_Pos (8U)
11301#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos)
11302#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk
11303#define PWR_PDCRD_PD7_Pos (7U)
11304#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos)
11305#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk
11306#define PWR_PDCRD_PD6_Pos (6U)
11307#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos)
11308#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk
11309#define PWR_PDCRD_PD5_Pos (5U)
11310#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos)
11311#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk
11312#define PWR_PDCRD_PD4_Pos (4U)
11313#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos)
11314#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk
11315#define PWR_PDCRD_PD3_Pos (3U)
11316#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)
11317#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk
11318#define PWR_PDCRD_PD2_Pos (2U)
11319#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)
11320#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk
11321#define PWR_PDCRD_PD1_Pos (1U)
11322#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)
11323#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk
11324#define PWR_PDCRD_PD0_Pos (0U)
11325#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)
11326#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk
11328/******************** Bit definition for PWR_PUCRE register ********************/
11329#define PWR_PUCRE_PE15_Pos (15U)
11330#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos)
11331#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk
11332#define PWR_PUCRE_PE14_Pos (14U)
11333#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos)
11334#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk
11335#define PWR_PUCRE_PE13_Pos (13U)
11336#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos)
11337#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk
11338#define PWR_PUCRE_PE12_Pos (12U)
11339#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos)
11340#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk
11341#define PWR_PUCRE_PE11_Pos (11U)
11342#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos)
11343#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk
11344#define PWR_PUCRE_PE10_Pos (10U)
11345#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos)
11346#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk
11347#define PWR_PUCRE_PE9_Pos (9U)
11348#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos)
11349#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk
11350#define PWR_PUCRE_PE8_Pos (8U)
11351#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos)
11352#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk
11353#define PWR_PUCRE_PE7_Pos (7U)
11354#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos)
11355#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk
11356#define PWR_PUCRE_PE6_Pos (6U)
11357#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos)
11358#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk
11359#define PWR_PUCRE_PE5_Pos (5U)
11360#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos)
11361#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk
11362#define PWR_PUCRE_PE4_Pos (4U)
11363#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos)
11364#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk
11365#define PWR_PUCRE_PE3_Pos (3U)
11366#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos)
11367#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk
11368#define PWR_PUCRE_PE2_Pos (2U)
11369#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos)
11370#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk
11371#define PWR_PUCRE_PE1_Pos (1U)
11372#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos)
11373#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk
11374#define PWR_PUCRE_PE0_Pos (0U)
11375#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos)
11376#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk
11378/******************** Bit definition for PWR_PDCRE register ********************/
11379#define PWR_PDCRE_PE15_Pos (15U)
11380#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos)
11381#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk
11382#define PWR_PDCRE_PE14_Pos (14U)
11383#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos)
11384#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk
11385#define PWR_PDCRE_PE13_Pos (13U)
11386#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos)
11387#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk
11388#define PWR_PDCRE_PE12_Pos (12U)
11389#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos)
11390#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk
11391#define PWR_PDCRE_PE11_Pos (11U)
11392#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos)
11393#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk
11394#define PWR_PDCRE_PE10_Pos (10U)
11395#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos)
11396#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk
11397#define PWR_PDCRE_PE9_Pos (9U)
11398#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos)
11399#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk
11400#define PWR_PDCRE_PE8_Pos (8U)
11401#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos)
11402#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk
11403#define PWR_PDCRE_PE7_Pos (7U)
11404#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos)
11405#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk
11406#define PWR_PDCRE_PE6_Pos (6U)
11407#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos)
11408#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk
11409#define PWR_PDCRE_PE5_Pos (5U)
11410#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos)
11411#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk
11412#define PWR_PDCRE_PE4_Pos (4U)
11413#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos)
11414#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk
11415#define PWR_PDCRE_PE3_Pos (3U)
11416#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos)
11417#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk
11418#define PWR_PDCRE_PE2_Pos (2U)
11419#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos)
11420#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk
11421#define PWR_PDCRE_PE1_Pos (1U)
11422#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos)
11423#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk
11424#define PWR_PDCRE_PE0_Pos (0U)
11425#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos)
11426#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk
11428/******************** Bit definition for PWR_PUCRF register ********************/
11429#define PWR_PUCRF_PF15_Pos (15U)
11430#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos)
11431#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk
11432#define PWR_PUCRF_PF14_Pos (14U)
11433#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos)
11434#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk
11435#define PWR_PUCRF_PF13_Pos (13U)
11436#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos)
11437#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk
11438#define PWR_PUCRF_PF12_Pos (12U)
11439#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos)
11440#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk
11441#define PWR_PUCRF_PF11_Pos (11U)
11442#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos)
11443#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk
11444#define PWR_PUCRF_PF10_Pos (10U)
11445#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos)
11446#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk
11447#define PWR_PUCRF_PF9_Pos (9U)
11448#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos)
11449#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk
11450#define PWR_PUCRF_PF8_Pos (8U)
11451#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos)
11452#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk
11453#define PWR_PUCRF_PF7_Pos (7U)
11454#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos)
11455#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk
11456#define PWR_PUCRF_PF6_Pos (6U)
11457#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos)
11458#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk
11459#define PWR_PUCRF_PF5_Pos (5U)
11460#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos)
11461#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk
11462#define PWR_PUCRF_PF4_Pos (4U)
11463#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos)
11464#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk
11465#define PWR_PUCRF_PF3_Pos (3U)
11466#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos)
11467#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk
11468#define PWR_PUCRF_PF2_Pos (2U)
11469#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos)
11470#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk
11471#define PWR_PUCRF_PF1_Pos (1U)
11472#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos)
11473#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk
11474#define PWR_PUCRF_PF0_Pos (0U)
11475#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos)
11476#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk
11478/******************** Bit definition for PWR_PDCRF register ********************/
11479#define PWR_PDCRF_PF15_Pos (15U)
11480#define PWR_PDCRF_PF15_Msk (0x1UL << PWR_PDCRF_PF15_Pos)
11481#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk
11482#define PWR_PDCRF_PF14_Pos (14U)
11483#define PWR_PDCRF_PF14_Msk (0x1UL << PWR_PDCRF_PF14_Pos)
11484#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk
11485#define PWR_PDCRF_PF13_Pos (13U)
11486#define PWR_PDCRF_PF13_Msk (0x1UL << PWR_PDCRF_PF13_Pos)
11487#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk
11488#define PWR_PDCRF_PF12_Pos (12U)
11489#define PWR_PDCRF_PF12_Msk (0x1UL << PWR_PDCRF_PF12_Pos)
11490#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk
11491#define PWR_PDCRF_PF11_Pos (11U)
11492#define PWR_PDCRF_PF11_Msk (0x1UL << PWR_PDCRF_PF11_Pos)
11493#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk
11494#define PWR_PDCRF_PF10_Pos (10U)
11495#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos)
11496#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk
11497#define PWR_PDCRF_PF9_Pos (9U)
11498#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos)
11499#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk
11500#define PWR_PDCRF_PF8_Pos (8U)
11501#define PWR_PDCRF_PF8_Msk (0x1UL << PWR_PDCRF_PF8_Pos)
11502#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk
11503#define PWR_PDCRF_PF7_Pos (7U)
11504#define PWR_PDCRF_PF7_Msk (0x1UL << PWR_PDCRF_PF7_Pos)
11505#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk
11506#define PWR_PDCRF_PF6_Pos (6U)
11507#define PWR_PDCRF_PF6_Msk (0x1UL << PWR_PDCRF_PF6_Pos)
11508#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk
11509#define PWR_PDCRF_PF5_Pos (5U)
11510#define PWR_PDCRF_PF5_Msk (0x1UL << PWR_PDCRF_PF5_Pos)
11511#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk
11512#define PWR_PDCRF_PF4_Pos (4U)
11513#define PWR_PDCRF_PF4_Msk (0x1UL << PWR_PDCRF_PF4_Pos)
11514#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk
11515#define PWR_PDCRF_PF3_Pos (3U)
11516#define PWR_PDCRF_PF3_Msk (0x1UL << PWR_PDCRF_PF3_Pos)
11517#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk
11518#define PWR_PDCRF_PF2_Pos (2U)
11519#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos)
11520#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk
11521#define PWR_PDCRF_PF1_Pos (1U)
11522#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos)
11523#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk
11524#define PWR_PDCRF_PF0_Pos (0U)
11525#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos)
11526#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk
11528/******************** Bit definition for PWR_PUCRG register ********************/
11529#define PWR_PUCRG_PG15_Pos (15U)
11530#define PWR_PUCRG_PG15_Msk (0x1UL << PWR_PUCRG_PG15_Pos)
11531#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk
11532#define PWR_PUCRG_PG14_Pos (14U)
11533#define PWR_PUCRG_PG14_Msk (0x1UL << PWR_PUCRG_PG14_Pos)
11534#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk
11535#define PWR_PUCRG_PG13_Pos (13U)
11536#define PWR_PUCRG_PG13_Msk (0x1UL << PWR_PUCRG_PG13_Pos)
11537#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk
11538#define PWR_PUCRG_PG12_Pos (12U)
11539#define PWR_PUCRG_PG12_Msk (0x1UL << PWR_PUCRG_PG12_Pos)
11540#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk
11541#define PWR_PUCRG_PG11_Pos (11U)
11542#define PWR_PUCRG_PG11_Msk (0x1UL << PWR_PUCRG_PG11_Pos)
11543#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk
11544#define PWR_PUCRG_PG10_Pos (10U)
11545#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos)
11546#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk
11547#define PWR_PUCRG_PG9_Pos (9U)
11548#define PWR_PUCRG_PG9_Msk (0x1UL << PWR_PUCRG_PG9_Pos)
11549#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk
11550#define PWR_PUCRG_PG8_Pos (8U)
11551#define PWR_PUCRG_PG8_Msk (0x1UL << PWR_PUCRG_PG8_Pos)
11552#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk
11553#define PWR_PUCRG_PG7_Pos (7U)
11554#define PWR_PUCRG_PG7_Msk (0x1UL << PWR_PUCRG_PG7_Pos)
11555#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk
11556#define PWR_PUCRG_PG6_Pos (6U)
11557#define PWR_PUCRG_PG6_Msk (0x1UL << PWR_PUCRG_PG6_Pos)
11558#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk
11559#define PWR_PUCRG_PG5_Pos (5U)
11560#define PWR_PUCRG_PG5_Msk (0x1UL << PWR_PUCRG_PG5_Pos)
11561#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk
11562#define PWR_PUCRG_PG4_Pos (4U)
11563#define PWR_PUCRG_PG4_Msk (0x1UL << PWR_PUCRG_PG4_Pos)
11564#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk
11565#define PWR_PUCRG_PG3_Pos (3U)
11566#define PWR_PUCRG_PG3_Msk (0x1UL << PWR_PUCRG_PG3_Pos)
11567#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk
11568#define PWR_PUCRG_PG2_Pos (2U)
11569#define PWR_PUCRG_PG2_Msk (0x1UL << PWR_PUCRG_PG2_Pos)
11570#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk
11571#define PWR_PUCRG_PG1_Pos (1U)
11572#define PWR_PUCRG_PG1_Msk (0x1UL << PWR_PUCRG_PG1_Pos)
11573#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk
11574#define PWR_PUCRG_PG0_Pos (0U)
11575#define PWR_PUCRG_PG0_Msk (0x1UL << PWR_PUCRG_PG0_Pos)
11576#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk
11578/******************** Bit definition for PWR_PDCRG register ********************/
11579#define PWR_PDCRG_PG10_Pos (10U)
11580#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos)
11581#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk
11582#define PWR_PDCRG_PG9_Pos (9U)
11583#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos)
11584#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk
11585#define PWR_PDCRG_PG8_Pos (8U)
11586#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos)
11587#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk
11588#define PWR_PDCRG_PG7_Pos (7U)
11589#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos)
11590#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk
11591#define PWR_PDCRG_PG6_Pos (6U)
11592#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos)
11593#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk
11594#define PWR_PDCRG_PG5_Pos (5U)
11595#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos)
11596#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk
11597#define PWR_PDCRG_PG4_Pos (4U)
11598#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos)
11599#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk
11600#define PWR_PDCRG_PG3_Pos (3U)
11601#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos)
11602#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk
11603#define PWR_PDCRG_PG2_Pos (2U)
11604#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos)
11605#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk
11606#define PWR_PDCRG_PG1_Pos (1U)
11607#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos)
11608#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk
11609#define PWR_PDCRG_PG0_Pos (0U)
11610#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos)
11611#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk
11613/******************** Bit definition for PWR_CR5 register ********************/
11614#define PWR_CR5_R1MODE_Pos (8U)
11615#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos)
11616#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk
11618/******************************************************************************/
11619/* */
11620/* QUADSPI */
11621/* */
11622/******************************************************************************/
11623/***************** Bit definition for QUADSPI_CR register *******************/
11624#define QUADSPI_CR_EN_Pos (0U)
11625#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
11626#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
11627#define QUADSPI_CR_ABORT_Pos (1U)
11628#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
11629#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
11630#define QUADSPI_CR_DMAEN_Pos (2U)
11631#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
11632#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
11633#define QUADSPI_CR_TCEN_Pos (3U)
11634#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
11635#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
11636#define QUADSPI_CR_SSHIFT_Pos (4U)
11637#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
11638#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
11639#define QUADSPI_CR_DFM_Pos (6U)
11640#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
11641#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
11642#define QUADSPI_CR_FSEL_Pos (7U)
11643#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
11644#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
11645#define QUADSPI_CR_FTHRES_Pos (8U)
11646#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos)
11647#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
11648#define QUADSPI_CR_TEIE_Pos (16U)
11649#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
11650#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
11651#define QUADSPI_CR_TCIE_Pos (17U)
11652#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
11653#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
11654#define QUADSPI_CR_FTIE_Pos (18U)
11655#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
11656#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
11657#define QUADSPI_CR_SMIE_Pos (19U)
11658#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
11659#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
11660#define QUADSPI_CR_TOIE_Pos (20U)
11661#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
11662#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
11663#define QUADSPI_CR_APMS_Pos (22U)
11664#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
11665#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
11666#define QUADSPI_CR_PMM_Pos (23U)
11667#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
11668#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
11669#define QUADSPI_CR_PRESCALER_Pos (24U)
11670#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
11671#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
11673/***************** Bit definition for QUADSPI_DCR register ******************/
11674#define QUADSPI_DCR_CKMODE_Pos (0U)
11675#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
11676#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
11677#define QUADSPI_DCR_CSHT_Pos (8U)
11678#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
11679#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
11680#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
11681#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
11682#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
11683#define QUADSPI_DCR_FSIZE_Pos (16U)
11684#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
11685#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
11687/****************** Bit definition for QUADSPI_SR register *******************/
11688#define QUADSPI_SR_TEF_Pos (0U)
11689#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
11690#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
11691#define QUADSPI_SR_TCF_Pos (1U)
11692#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
11693#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
11694#define QUADSPI_SR_FTF_Pos (2U)
11695#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
11696#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
11697#define QUADSPI_SR_SMF_Pos (3U)
11698#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
11699#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
11700#define QUADSPI_SR_TOF_Pos (4U)
11701#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
11702#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
11703#define QUADSPI_SR_BUSY_Pos (5U)
11704#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
11705#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
11706#define QUADSPI_SR_FLEVEL_Pos (8U)
11707#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos)
11708#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
11710/****************** Bit definition for QUADSPI_FCR register ******************/
11711#define QUADSPI_FCR_CTEF_Pos (0U)
11712#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
11713#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
11714#define QUADSPI_FCR_CTCF_Pos (1U)
11715#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
11716#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
11717#define QUADSPI_FCR_CSMF_Pos (3U)
11718#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
11719#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
11720#define QUADSPI_FCR_CTOF_Pos (4U)
11721#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
11722#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
11724/****************** Bit definition for QUADSPI_DLR register ******************/
11725#define QUADSPI_DLR_DL_Pos (0U)
11726#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
11727#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
11729/****************** Bit definition for QUADSPI_CCR register ******************/
11730#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
11731#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
11732#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
11733#define QUADSPI_CCR_IMODE_Pos (8U)
11734#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
11735#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
11736#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
11737#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
11738#define QUADSPI_CCR_ADMODE_Pos (10U)
11739#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
11740#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
11741#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
11742#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
11743#define QUADSPI_CCR_ADSIZE_Pos (12U)
11744#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
11745#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
11746#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
11747#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
11748#define QUADSPI_CCR_ABMODE_Pos (14U)
11749#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
11750#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
11751#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
11752#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
11753#define QUADSPI_CCR_ABSIZE_Pos (16U)
11754#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
11755#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
11756#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
11757#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
11758#define QUADSPI_CCR_DCYC_Pos (18U)
11759#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
11760#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
11761#define QUADSPI_CCR_DMODE_Pos (24U)
11762#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
11763#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
11764#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
11765#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
11766#define QUADSPI_CCR_FMODE_Pos (26U)
11767#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
11768#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
11769#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
11770#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
11771#define QUADSPI_CCR_SIOO_Pos (28U)
11772#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
11773#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
11774#define QUADSPI_CCR_DHHC_Pos (30U)
11775#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
11776#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
11777#define QUADSPI_CCR_DDRM_Pos (31U)
11778#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
11779#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
11781/****************** Bit definition for QUADSPI_AR register *******************/
11782#define QUADSPI_AR_ADDRESS_Pos (0U)
11783#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
11784#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
11786/****************** Bit definition for QUADSPI_ABR register ******************/
11787#define QUADSPI_ABR_ALTERNATE_Pos (0U)
11788#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
11789#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
11791/****************** Bit definition for QUADSPI_DR register *******************/
11792#define QUADSPI_DR_DATA_Pos (0U)
11793#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
11794#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
11796/****************** Bit definition for QUADSPI_PSMKR register ****************/
11797#define QUADSPI_PSMKR_MASK_Pos (0U)
11798#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
11799#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
11801/****************** Bit definition for QUADSPI_PSMAR register ****************/
11802#define QUADSPI_PSMAR_MATCH_Pos (0U)
11803#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
11804#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
11806/****************** Bit definition for QUADSPI_PIR register *****************/
11807#define QUADSPI_PIR_INTERVAL_Pos (0U)
11808#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
11809#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
11811/****************** Bit definition for QUADSPI_LPTR register *****************/
11812#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
11813#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
11814#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
11816/******************************************************************************/
11817/* */
11818/* Reset and Clock Control */
11819/* */
11820/******************************************************************************/
11821/*
11822* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
11823*/
11824
11825#define RCC_HSI48_SUPPORT
11826#define RCC_PLLP_DIV_2_31_SUPPORT
11827
11828/******************** Bit definition for RCC_CR register ********************/
11829#define RCC_CR_HSION_Pos (8U)
11830#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
11831#define RCC_CR_HSION RCC_CR_HSION_Msk
11832#define RCC_CR_HSIKERON_Pos (9U)
11833#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
11834#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
11835#define RCC_CR_HSIRDY_Pos (10U)
11836#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
11837#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
11839#define RCC_CR_HSEON_Pos (16U)
11840#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
11841#define RCC_CR_HSEON RCC_CR_HSEON_Msk
11842#define RCC_CR_HSERDY_Pos (17U)
11843#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
11844#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
11845#define RCC_CR_HSEBYP_Pos (18U)
11846#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
11847#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
11848#define RCC_CR_CSSON_Pos (19U)
11849#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
11850#define RCC_CR_CSSON RCC_CR_CSSON_Msk
11852#define RCC_CR_PLLON_Pos (24U)
11853#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
11854#define RCC_CR_PLLON RCC_CR_PLLON_Msk
11855#define RCC_CR_PLLRDY_Pos (25U)
11856#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
11857#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
11859/******************** Bit definition for RCC_ICSCR register ***************/
11861#define RCC_ICSCR_HSICAL_Pos (16U)
11862#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)
11863#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk
11864#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)
11865#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)
11866#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)
11867#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)
11868#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)
11869#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)
11870#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)
11871#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)
11874#define RCC_ICSCR_HSITRIM_Pos (24U)
11875#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos)
11876#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk
11877#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)
11878#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)
11879#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)
11880#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)
11881#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)
11882#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos)
11883#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos)
11885/******************** Bit definition for RCC_CFGR register ******************/
11887#define RCC_CFGR_SW_Pos (0U)
11888#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
11889#define RCC_CFGR_SW RCC_CFGR_SW_Msk
11890#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
11891#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
11893#define RCC_CFGR_SW_HSI (0x00000001U)
11894#define RCC_CFGR_SW_HSE (0x00000002U)
11895#define RCC_CFGR_SW_PLL (0x00000003U)
11898#define RCC_CFGR_SWS_Pos (2U)
11899#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
11900#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
11901#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
11902#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
11904#define RCC_CFGR_SWS_HSI (0x00000004U)
11905#define RCC_CFGR_SWS_HSE (0x00000008U)
11906#define RCC_CFGR_SWS_PLL (0x0000000CU)
11909#define RCC_CFGR_HPRE_Pos (4U)
11910#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
11911#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
11912#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
11913#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
11914#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
11915#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
11917#define RCC_CFGR_HPRE_DIV1 (0x00000000U)
11918#define RCC_CFGR_HPRE_DIV2 (0x00000080U)
11919#define RCC_CFGR_HPRE_DIV4 (0x00000090U)
11920#define RCC_CFGR_HPRE_DIV8 (0x000000A0U)
11921#define RCC_CFGR_HPRE_DIV16 (0x000000B0U)
11922#define RCC_CFGR_HPRE_DIV64 (0x000000C0U)
11923#define RCC_CFGR_HPRE_DIV128 (0x000000D0U)
11924#define RCC_CFGR_HPRE_DIV256 (0x000000E0U)
11925#define RCC_CFGR_HPRE_DIV512 (0x000000F0U)
11928#define RCC_CFGR_PPRE1_Pos (8U)
11929#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
11930#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
11931#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
11932#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
11933#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
11935#define RCC_CFGR_PPRE1_DIV1 (0x00000000U)
11936#define RCC_CFGR_PPRE1_DIV2 (0x00000400U)
11937#define RCC_CFGR_PPRE1_DIV4 (0x00000500U)
11938#define RCC_CFGR_PPRE1_DIV8 (0x00000600U)
11939#define RCC_CFGR_PPRE1_DIV16 (0x00000700U)
11942#define RCC_CFGR_PPRE2_Pos (11U)
11943#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
11944#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
11945#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
11946#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
11947#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
11949#define RCC_CFGR_PPRE2_DIV1 (0x00000000U)
11950#define RCC_CFGR_PPRE2_DIV2 (0x00002000U)
11951#define RCC_CFGR_PPRE2_DIV4 (0x00002800U)
11952#define RCC_CFGR_PPRE2_DIV8 (0x00003000U)
11953#define RCC_CFGR_PPRE2_DIV16 (0x00003800U)
11956#define RCC_CFGR_MCOSEL_Pos (24U)
11957#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos)
11958#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk
11959#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)
11960#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)
11961#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)
11962#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos)
11964#define RCC_CFGR_MCOPRE_Pos (28U)
11965#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)
11966#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk
11967#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)
11968#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)
11969#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)
11971#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U)
11972#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U)
11973#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U)
11974#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U)
11975#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U)
11977/* Legacy aliases */
11978#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
11979#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
11980#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
11981#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
11982#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
11983#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
11984
11985/******************** Bit definition for RCC_PLLCFGR register ***************/
11986#define RCC_PLLCFGR_PLLSRC_Pos (0U)
11987#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)
11988#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
11989#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
11990#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)
11992#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
11993#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)
11994#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk
11995#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
11996#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
11997#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
11999#define RCC_PLLCFGR_PLLM_Pos (4U)
12000#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos)
12001#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
12002#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)
12003#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)
12004#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)
12005#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos)
12007#define RCC_PLLCFGR_PLLN_Pos (8U)
12008#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)
12009#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
12010#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)
12011#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)
12012#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)
12013#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)
12014#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)
12015#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)
12016#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)
12018#define RCC_PLLCFGR_PLLPEN_Pos (16U)
12019#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)
12020#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
12021#define RCC_PLLCFGR_PLLP_Pos (17U)
12022#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos)
12023#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
12024#define RCC_PLLCFGR_PLLQEN_Pos (20U)
12025#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)
12026#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
12027
12028#define RCC_PLLCFGR_PLLQ_Pos (21U)
12029#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos)
12030#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
12031#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
12032#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
12034#define RCC_PLLCFGR_PLLREN_Pos (24U)
12035#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)
12036#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
12037#define RCC_PLLCFGR_PLLR_Pos (25U)
12038#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos)
12039#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
12040#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
12041#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
12043#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
12044#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)
12045#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
12046#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)
12047#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)
12048#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)
12049#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)
12050#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)
12052/******************** Bit definition for RCC_CIER register ******************/
12053#define RCC_CIER_LSIRDYIE_Pos (0U)
12054#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
12055#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
12056#define RCC_CIER_LSERDYIE_Pos (1U)
12057#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
12058#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
12059#define RCC_CIER_HSIRDYIE_Pos (3U)
12060#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
12061#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
12062#define RCC_CIER_HSERDYIE_Pos (4U)
12063#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
12064#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
12065#define RCC_CIER_PLLRDYIE_Pos (5U)
12066#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)
12067#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
12068#define RCC_CIER_LSECSSIE_Pos (9U)
12069#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
12070#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
12071#define RCC_CIER_HSI48RDYIE_Pos (10U)
12072#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
12073#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
12074
12075/******************** Bit definition for RCC_CIFR register ******************/
12076#define RCC_CIFR_LSIRDYF_Pos (0U)
12077#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
12078#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
12079#define RCC_CIFR_LSERDYF_Pos (1U)
12080#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
12081#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
12082#define RCC_CIFR_HSIRDYF_Pos (3U)
12083#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
12084#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
12085#define RCC_CIFR_HSERDYF_Pos (4U)
12086#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
12087#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
12088#define RCC_CIFR_PLLRDYF_Pos (5U)
12089#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
12090#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
12091#define RCC_CIFR_CSSF_Pos (8U)
12092#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)
12093#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
12094#define RCC_CIFR_LSECSSF_Pos (9U)
12095#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
12096#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
12097#define RCC_CIFR_HSI48RDYF_Pos (10U)
12098#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
12099#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
12100
12101/******************** Bit definition for RCC_CICR register ******************/
12102#define RCC_CICR_LSIRDYC_Pos (0U)
12103#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
12104#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
12105#define RCC_CICR_LSERDYC_Pos (1U)
12106#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
12107#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
12108#define RCC_CICR_HSIRDYC_Pos (3U)
12109#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
12110#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
12111#define RCC_CICR_HSERDYC_Pos (4U)
12112#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
12113#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
12114#define RCC_CICR_PLLRDYC_Pos (5U)
12115#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
12116#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
12117#define RCC_CICR_CSSC_Pos (8U)
12118#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)
12119#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
12120#define RCC_CICR_LSECSSC_Pos (9U)
12121#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
12122#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
12123#define RCC_CICR_HSI48RDYC_Pos (10U)
12124#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
12125#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
12126
12127/******************** Bit definition for RCC_AHB1RSTR register **************/
12128#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
12129#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
12130#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
12131#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
12132#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
12133#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
12134#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
12135#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)
12136#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
12137#define RCC_AHB1RSTR_CORDICRST_Pos (3U)
12138#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)
12139#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
12140#define RCC_AHB1RSTR_FMACRST_Pos (4U)
12141#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)
12142#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
12143#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
12144#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)
12145#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
12146#define RCC_AHB1RSTR_CRCRST_Pos (12U)
12147#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
12148#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
12149
12150/******************** Bit definition for RCC_AHB2RSTR register **************/
12151#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
12152#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)
12153#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
12154#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
12155#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)
12156#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
12157#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
12158#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)
12159#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
12160#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
12161#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)
12162#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
12163#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
12164#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)
12165#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
12166#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
12167#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)
12168#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
12169#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
12170#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)
12171#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
12172#define RCC_AHB2RSTR_ADC12RST_Pos (13U)
12173#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)
12174#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
12175#define RCC_AHB2RSTR_ADC345RST_Pos (14U)
12176#define RCC_AHB2RSTR_ADC345RST_Msk (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)
12177#define RCC_AHB2RSTR_ADC345RST RCC_AHB2RSTR_ADC345RST_Msk
12178#define RCC_AHB2RSTR_DAC1RST_Pos (16U)
12179#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)
12180#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
12181#define RCC_AHB2RSTR_DAC2RST_Pos (17U)
12182#define RCC_AHB2RSTR_DAC2RST_Msk (0x1UL << RCC_AHB2RSTR_DAC2RST_Pos)
12183#define RCC_AHB2RSTR_DAC2RST RCC_AHB2RSTR_DAC2RST_Msk
12184#define RCC_AHB2RSTR_DAC3RST_Pos (18U)
12185#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)
12186#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
12187#define RCC_AHB2RSTR_DAC4RST_Pos (19U)
12188#define RCC_AHB2RSTR_DAC4RST_Msk (0x1UL << RCC_AHB2RSTR_DAC4RST_Pos)
12189#define RCC_AHB2RSTR_DAC4RST RCC_AHB2RSTR_DAC4RST_Msk
12190#define RCC_AHB2RSTR_RNGRST_Pos (26U)
12191#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
12192#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
12193
12194/******************** Bit definition for RCC_AHB3RSTR register **************/
12195#define RCC_AHB3RSTR_FMCRST_Pos (0U)
12196#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
12197#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
12198#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
12199#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
12200#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
12201
12202/******************** Bit definition for RCC_APB1RSTR1 register **************/
12203#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
12204#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)
12205#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
12206#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
12207#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)
12208#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
12209#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
12210#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)
12211#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
12212#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
12213#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)
12214#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
12215#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
12216#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)
12217#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
12218#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
12219#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)
12220#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
12221#define RCC_APB1RSTR1_CRSRST_Pos (8U)
12222#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)
12223#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
12224#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
12225#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)
12226#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
12227#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
12228#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)
12229#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
12230#define RCC_APB1RSTR1_USART2RST_Pos (17U)
12231#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)
12232#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
12233#define RCC_APB1RSTR1_USART3RST_Pos (18U)
12234#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)
12235#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
12236#define RCC_APB1RSTR1_UART4RST_Pos (19U)
12237#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)
12238#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
12239#define RCC_APB1RSTR1_UART5RST_Pos (20U)
12240#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)
12241#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
12242#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
12243#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)
12244#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
12245#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
12246#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)
12247#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
12248#define RCC_APB1RSTR1_USBRST_Pos (23U)
12249#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)
12250#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
12251#define RCC_APB1RSTR1_FDCANRST_Pos (25U)
12252#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)
12253#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
12254#define RCC_APB1RSTR1_PWRRST_Pos (28U)
12255#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)
12256#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
12257#define RCC_APB1RSTR1_I2C3RST_Pos (30U)
12258#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)
12259#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
12260#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
12261#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)
12262#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
12263
12264/******************** Bit definition for RCC_APB1RSTR2 register **************/
12265#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
12266#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)
12267#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
12268#define RCC_APB1RSTR2_I2C4RST_Pos (1U)
12269#define RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)
12270#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
12271#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
12272#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)
12273#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
12274
12275/******************** Bit definition for RCC_APB2RSTR register **************/
12276#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
12277#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
12278#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
12279#define RCC_APB2RSTR_TIM1RST_Pos (11U)
12280#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
12281#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
12282#define RCC_APB2RSTR_SPI1RST_Pos (12U)
12283#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
12284#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
12285#define RCC_APB2RSTR_TIM8RST_Pos (13U)
12286#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
12287#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
12288#define RCC_APB2RSTR_USART1RST_Pos (14U)
12289#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
12290#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
12291#define RCC_APB2RSTR_SPI4RST_Pos (15U)
12292#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
12293#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
12294#define RCC_APB2RSTR_TIM15RST_Pos (16U)
12295#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
12296#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
12297#define RCC_APB2RSTR_TIM16RST_Pos (17U)
12298#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
12299#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
12300#define RCC_APB2RSTR_TIM17RST_Pos (18U)
12301#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
12302#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
12303#define RCC_APB2RSTR_TIM20RST_Pos (20U)
12304#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)
12305#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
12306#define RCC_APB2RSTR_SAI1RST_Pos (21U)
12307#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
12308#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
12309#define RCC_APB2RSTR_HRTIM1RST_Pos (26U)
12310#define RCC_APB2RSTR_HRTIM1RST_Msk (0x1UL << RCC_APB2RSTR_HRTIM1RST_Pos)
12311#define RCC_APB2RSTR_HRTIM1RST RCC_APB2RSTR_HRTIM1RST_Msk
12312
12313/******************** Bit definition for RCC_AHB1ENR register ***************/
12314#define RCC_AHB1ENR_DMA1EN_Pos (0U)
12315#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
12316#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
12317#define RCC_AHB1ENR_DMA2EN_Pos (1U)
12318#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
12319#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
12320#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
12321#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)
12322#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
12323#define RCC_AHB1ENR_CORDICEN_Pos (3U)
12324#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)
12325#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
12326#define RCC_AHB1ENR_FMACEN_Pos (4U)
12327#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos)
12328#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
12329#define RCC_AHB1ENR_FLASHEN_Pos (8U)
12330#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)
12331#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
12332#define RCC_AHB1ENR_CRCEN_Pos (12U)
12333#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
12334#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
12335
12336/******************** Bit definition for RCC_AHB2ENR register ***************/
12337#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
12338#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)
12339#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
12340#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
12341#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)
12342#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
12343#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
12344#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)
12345#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
12346#define RCC_AHB2ENR_GPIODEN_Pos (3U)
12347#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)
12348#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
12349#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
12350#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)
12351#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
12352#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
12353#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)
12354#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
12355#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
12356#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)
12357#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
12358#define RCC_AHB2ENR_ADC12EN_Pos (13U)
12359#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)
12360#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
12361#define RCC_AHB2ENR_ADC345EN_Pos (14U)
12362#define RCC_AHB2ENR_ADC345EN_Msk (0x1UL << RCC_AHB2ENR_ADC345EN_Pos)
12363#define RCC_AHB2ENR_ADC345EN RCC_AHB2ENR_ADC345EN_Msk
12364#define RCC_AHB2ENR_DAC1EN_Pos (16U)
12365#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)
12366#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
12367#define RCC_AHB2ENR_DAC2EN_Pos (17U)
12368#define RCC_AHB2ENR_DAC2EN_Msk (0x1UL << RCC_AHB2ENR_DAC2EN_Pos)
12369#define RCC_AHB2ENR_DAC2EN RCC_AHB2ENR_DAC2EN_Msk
12370#define RCC_AHB2ENR_DAC3EN_Pos (18U)
12371#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)
12372#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
12373#define RCC_AHB2ENR_DAC4EN_Pos (19U)
12374#define RCC_AHB2ENR_DAC4EN_Msk (0x1UL << RCC_AHB2ENR_DAC4EN_Pos)
12375#define RCC_AHB2ENR_DAC4EN RCC_AHB2ENR_DAC4EN_Msk
12376#define RCC_AHB2ENR_RNGEN_Pos (26U)
12377#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
12378#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
12379
12380/******************** Bit definition for RCC_AHB3ENR register ***************/
12381#define RCC_AHB3ENR_FMCEN_Pos (0U)
12382#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
12383#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
12384#define RCC_AHB3ENR_QSPIEN_Pos (8U)
12385#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
12386#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
12387
12388/******************** Bit definition for RCC_APB1ENR1 register ***************/
12389#define RCC_APB1ENR1_TIM2EN_Pos (0U)
12390#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)
12391#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
12392#define RCC_APB1ENR1_TIM3EN_Pos (1U)
12393#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)
12394#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
12395#define RCC_APB1ENR1_TIM4EN_Pos (2U)
12396#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)
12397#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
12398#define RCC_APB1ENR1_TIM5EN_Pos (3U)
12399#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)
12400#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
12401#define RCC_APB1ENR1_TIM6EN_Pos (4U)
12402#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)
12403#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
12404#define RCC_APB1ENR1_TIM7EN_Pos (5U)
12405#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)
12406#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
12407#define RCC_APB1ENR1_CRSEN_Pos (8U)
12408#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos)
12409#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
12410#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
12411#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)
12412#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
12413#define RCC_APB1ENR1_WWDGEN_Pos (11U)
12414#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)
12415#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
12416#define RCC_APB1ENR1_SPI2EN_Pos (14U)
12417#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)
12418#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
12419#define RCC_APB1ENR1_SPI3EN_Pos (15U)
12420#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)
12421#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
12422#define RCC_APB1ENR1_USART2EN_Pos (17U)
12423#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)
12424#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
12425#define RCC_APB1ENR1_USART3EN_Pos (18U)
12426#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)
12427#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
12428#define RCC_APB1ENR1_UART4EN_Pos (19U)
12429#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)
12430#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
12431#define RCC_APB1ENR1_UART5EN_Pos (20U)
12432#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)
12433#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
12434#define RCC_APB1ENR1_I2C1EN_Pos (21U)
12435#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)
12436#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
12437#define RCC_APB1ENR1_I2C2EN_Pos (22U)
12438#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)
12439#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
12440#define RCC_APB1ENR1_USBEN_Pos (23U)
12441#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)
12442#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
12443#define RCC_APB1ENR1_FDCANEN_Pos (25U)
12444#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)
12445#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
12446#define RCC_APB1ENR1_PWREN_Pos (28U)
12447#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos)
12448#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
12449#define RCC_APB1ENR1_I2C3EN_Pos (30U)
12450#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)
12451#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
12452#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
12453#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)
12454#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
12455
12456/******************** Bit definition for RCC_APB1RSTR2 register **************/
12457#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
12458#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)
12459#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
12460#define RCC_APB1ENR2_I2C4EN_Pos (1U)
12461#define RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)
12462#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
12463#define RCC_APB1ENR2_UCPD1EN_Pos (8U)
12464#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)
12465#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
12466
12467/******************** Bit definition for RCC_APB2ENR register ***************/
12468#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
12469#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
12470#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
12471#define RCC_APB2ENR_TIM1EN_Pos (11U)
12472#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
12473#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
12474#define RCC_APB2ENR_SPI1EN_Pos (12U)
12475#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
12476#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
12477#define RCC_APB2ENR_TIM8EN_Pos (13U)
12478#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
12479#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
12480#define RCC_APB2ENR_USART1EN_Pos (14U)
12481#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
12482#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
12483#define RCC_APB2ENR_SPI4EN_Pos (15U)
12484#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
12485#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
12486#define RCC_APB2ENR_TIM15EN_Pos (16U)
12487#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
12488#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
12489#define RCC_APB2ENR_TIM16EN_Pos (17U)
12490#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
12491#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
12492#define RCC_APB2ENR_TIM17EN_Pos (18U)
12493#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
12494#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
12495#define RCC_APB2ENR_TIM20EN_Pos (20U)
12496#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)
12497#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
12498#define RCC_APB2ENR_SAI1EN_Pos (21U)
12499#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
12500#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
12501#define RCC_APB2ENR_HRTIM1EN_Pos (26U)
12502#define RCC_APB2ENR_HRTIM1EN_Msk (0x1UL << RCC_APB2ENR_HRTIM1EN_Pos)
12503#define RCC_APB2ENR_HRTIM1EN RCC_APB2ENR_HRTIM1EN_Msk
12504
12505/******************** Bit definition for RCC_AHB1SMENR register ***************/
12506#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
12507#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)
12508#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
12509#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
12510#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)
12511#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
12512#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
12513#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)
12514#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
12515#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
12516#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)
12517#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
12518#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
12519#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)
12520#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
12521#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
12522#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)
12523#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
12524#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
12525#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)
12526#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
12527#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
12528#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)
12529#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
12530
12531/******************** Bit definition for RCC_AHB2SMENR register *************/
12532#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
12533#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)
12534#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
12535#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
12536#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)
12537#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
12538#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
12539#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)
12540#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
12541#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
12542#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)
12543#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
12544#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
12545#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)
12546#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
12547#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
12548#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)
12549#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
12550#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
12551#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)
12552#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
12553#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
12554#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)
12555#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
12556#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
12557#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)
12558#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
12559#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
12560#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)
12561#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
12562#define RCC_AHB2SMENR_ADC345SMEN_Pos (14U)
12563#define RCC_AHB2SMENR_ADC345SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)
12564#define RCC_AHB2SMENR_ADC345SMEN RCC_AHB2SMENR_ADC345SMEN_Msk
12565#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
12566#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)
12567#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
12568#define RCC_AHB2SMENR_DAC2SMEN_Pos (17U)
12569#define RCC_AHB2SMENR_DAC2SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC2SMEN_Pos)
12570#define RCC_AHB2SMENR_DAC2SMEN RCC_AHB2SMENR_DAC2SMEN_Msk
12571#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
12572#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)
12573#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
12574#define RCC_AHB2SMENR_DAC4SMEN_Pos (19U)
12575#define RCC_AHB2SMENR_DAC4SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC4SMEN_Pos)
12576#define RCC_AHB2SMENR_DAC4SMEN RCC_AHB2SMENR_DAC4SMEN_Msk
12577#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
12578#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)
12579#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
12580
12581/******************** Bit definition for RCC_AHB3SMENR register *************/
12582#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
12583#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)
12584#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
12585#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
12586#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)
12587#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
12588
12589/******************** Bit definition for RCC_APB1SMENR1 register *************/
12590#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
12591#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)
12592#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
12593#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
12594#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)
12595#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
12596#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
12597#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)
12598#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
12599#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
12600#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)
12601#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
12602#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
12603#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)
12604#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
12605#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
12606#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)
12607#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
12608#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
12609#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)
12610#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
12611#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
12612#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)
12613#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
12614#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
12615#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)
12616#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
12617#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
12618#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)
12619#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
12620#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
12621#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)
12622#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
12623#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
12624#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)
12625#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
12626#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
12627#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)
12628#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
12629#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
12630#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)
12631#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
12632#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
12633#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)
12634#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
12635#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
12636#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)
12637#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
12638#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
12639#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)
12640#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
12641#define RCC_APB1SMENR1_USBSMEN_Pos (23U)
12642#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)
12643#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
12644#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
12645#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)
12646#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
12647#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
12648#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)
12649#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
12650#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
12651#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)
12652#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
12653#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
12654#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)
12655#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
12656
12657/******************** Bit definition for RCC_APB1SMENR2 register *************/
12658#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
12659#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)
12660#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
12661#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
12662#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)
12663#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
12664#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
12665#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)
12666#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
12667
12668/******************** Bit definition for RCC_APB2SMENR register *************/
12669#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
12670#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)
12671#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
12672#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
12673#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)
12674#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
12675#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
12676#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)
12677#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
12678#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
12679#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)
12680#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
12681#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
12682#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)
12683#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
12684#define RCC_APB2SMENR_SPI4SMEN_Pos (15U)
12685#define RCC_APB2SMENR_SPI4SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI4SMEN_Pos)
12686#define RCC_APB2SMENR_SPI4SMEN RCC_APB2SMENR_SPI4SMEN_Msk
12687#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
12688#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)
12689#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
12690#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
12691#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)
12692#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
12693#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
12694#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)
12695#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
12696#define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
12697#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)
12698#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
12699#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
12700#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)
12701#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
12702#define RCC_APB2SMENR_HRTIM1SMEN_Pos (26U)
12703#define RCC_APB2SMENR_HRTIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_HRTIM1SMEN_Pos)
12704#define RCC_APB2SMENR_HRTIM1SMEN RCC_APB2SMENR_HRTIM1SMEN_Msk
12705
12706/******************** Bit definition for RCC_CCIPR register ******************/
12707#define RCC_CCIPR_USART1SEL_Pos (0U)
12708#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)
12709#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
12710#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)
12711#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)
12713#define RCC_CCIPR_USART2SEL_Pos (2U)
12714#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)
12715#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
12716#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)
12717#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)
12719#define RCC_CCIPR_USART3SEL_Pos (4U)
12720#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)
12721#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
12722#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)
12723#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)
12725#define RCC_CCIPR_UART4SEL_Pos (6U)
12726#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos)
12727#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
12728#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos)
12729#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos)
12731#define RCC_CCIPR_UART5SEL_Pos (8U)
12732#define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos)
12733#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
12734#define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos)
12735#define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos)
12737#define RCC_CCIPR_LPUART1SEL_Pos (10U)
12738#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)
12739#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
12740#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)
12741#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)
12743#define RCC_CCIPR_I2C1SEL_Pos (12U)
12744#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)
12745#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
12746#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)
12747#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)
12749#define RCC_CCIPR_I2C2SEL_Pos (14U)
12750#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos)
12751#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
12752#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)
12753#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)
12755#define RCC_CCIPR_I2C3SEL_Pos (16U)
12756#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)
12757#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
12758#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)
12759#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)
12761#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
12762#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)
12763#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
12764#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)
12765#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)
12767#define RCC_CCIPR_SAI1SEL_Pos (20U)
12768#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)
12769#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
12770#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)
12771#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)
12773#define RCC_CCIPR_I2S23SEL_Pos (22U)
12774#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)
12775#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
12776#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)
12777#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)
12779#define RCC_CCIPR_FDCANSEL_Pos (24U)
12780#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos)
12781#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
12782#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos)
12783#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos)
12785#define RCC_CCIPR_CLK48SEL_Pos (26U)
12786#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos)
12787#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
12788#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos)
12789#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos)
12791#define RCC_CCIPR_ADC12SEL_Pos (28U)
12792#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos)
12793#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
12794#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)
12795#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)
12797#define RCC_CCIPR_ADC345SEL_Pos (30U)
12798#define RCC_CCIPR_ADC345SEL_Msk (0x3UL << RCC_CCIPR_ADC345SEL_Pos)
12799#define RCC_CCIPR_ADC345SEL RCC_CCIPR_ADC345SEL_Msk
12800#define RCC_CCIPR_ADC345SEL_0 (0x1UL << RCC_CCIPR_ADC345SEL_Pos)
12801#define RCC_CCIPR_ADC345SEL_1 (0x2UL << RCC_CCIPR_ADC345SEL_Pos)
12803/******************** Bit definition for RCC_BDCR register ******************/
12804#define RCC_BDCR_LSEON_Pos (0U)
12805#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
12806#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
12807#define RCC_BDCR_LSERDY_Pos (1U)
12808#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
12809#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
12810#define RCC_BDCR_LSEBYP_Pos (2U)
12811#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
12812#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
12813
12814#define RCC_BDCR_LSEDRV_Pos (3U)
12815#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
12816#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
12817#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
12818#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
12820#define RCC_BDCR_LSECSSON_Pos (5U)
12821#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
12822#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
12823#define RCC_BDCR_LSECSSD_Pos (6U)
12824#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
12825#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
12826
12827#define RCC_BDCR_RTCSEL_Pos (8U)
12828#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
12829#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
12830#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
12831#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
12833#define RCC_BDCR_RTCEN_Pos (15U)
12834#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
12835#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
12836#define RCC_BDCR_BDRST_Pos (16U)
12837#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
12838#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
12839#define RCC_BDCR_LSCOEN_Pos (24U)
12840#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)
12841#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
12842#define RCC_BDCR_LSCOSEL_Pos (25U)
12843#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)
12844#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
12845
12846/******************** Bit definition for RCC_CSR register *******************/
12847#define RCC_CSR_LSION_Pos (0U)
12848#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
12849#define RCC_CSR_LSION RCC_CSR_LSION_Msk
12850#define RCC_CSR_LSIRDY_Pos (1U)
12851#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
12852#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
12853
12854#define RCC_CSR_RMVF_Pos (23U)
12855#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
12856#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
12857#define RCC_CSR_OBLRSTF_Pos (25U)
12858#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)
12859#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
12860#define RCC_CSR_PINRSTF_Pos (26U)
12861#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
12862#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
12863#define RCC_CSR_BORRSTF_Pos (27U)
12864#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
12865#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
12866#define RCC_CSR_SFTRSTF_Pos (28U)
12867#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
12868#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
12869#define RCC_CSR_IWDGRSTF_Pos (29U)
12870#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
12871#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
12872#define RCC_CSR_WWDGRSTF_Pos (30U)
12873#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
12874#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
12875#define RCC_CSR_LPWRRSTF_Pos (31U)
12876#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
12877#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
12878
12879/******************** Bit definition for RCC_CRRCR register *****************/
12880#define RCC_CRRCR_HSI48ON_Pos (0U)
12881#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos)
12882#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
12883#define RCC_CRRCR_HSI48RDY_Pos (1U)
12884#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos)
12885#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
12886
12888#define RCC_CRRCR_HSI48CAL_Pos (7U)
12889#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)
12890#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
12891#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
12892#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
12893#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
12894#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
12895#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
12896#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
12897#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
12898#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
12899#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
12901/******************** Bit definition for RCC_CCIPR2 register ******************/
12902#define RCC_CCIPR2_I2C4SEL_Pos (0U)
12903#define RCC_CCIPR2_I2C4SEL_Msk (0x3UL << RCC_CCIPR2_I2C4SEL_Pos)
12904#define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
12905#define RCC_CCIPR2_I2C4SEL_0 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos)
12906#define RCC_CCIPR2_I2C4SEL_1 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos)
12908#define RCC_CCIPR2_QSPISEL_Pos (20U)
12909#define RCC_CCIPR2_QSPISEL_Msk (0x3UL << RCC_CCIPR2_QSPISEL_Pos)
12910#define RCC_CCIPR2_QSPISEL RCC_CCIPR2_QSPISEL_Msk
12911#define RCC_CCIPR2_QSPISEL_0 (0x1UL << RCC_CCIPR2_QSPISEL_Pos)
12912#define RCC_CCIPR2_QSPISEL_1 (0x2UL << RCC_CCIPR2_QSPISEL_Pos)
12914/******************************************************************************/
12915/* */
12916/* RNG */
12917/* */
12918/******************************************************************************/
12919/******************** Bits definition for RNG_CR register *******************/
12920#define RNG_CR_RNGEN_Pos (2U)
12921#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
12922#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
12923#define RNG_CR_IE_Pos (3U)
12924#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
12925#define RNG_CR_IE RNG_CR_IE_Msk
12926#define RNG_CR_CED_Pos (5U)
12927#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos)
12928#define RNG_CR_CED RNG_CR_IE_Msk
12929
12930/******************** Bits definition for RNG_SR register *******************/
12931#define RNG_SR_DRDY_Pos (0U)
12932#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
12933#define RNG_SR_DRDY RNG_SR_DRDY_Msk
12934#define RNG_SR_CECS_Pos (1U)
12935#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
12936#define RNG_SR_CECS RNG_SR_CECS_Msk
12937#define RNG_SR_SECS_Pos (2U)
12938#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
12939#define RNG_SR_SECS RNG_SR_SECS_Msk
12940#define RNG_SR_CEIS_Pos (5U)
12941#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
12942#define RNG_SR_CEIS RNG_SR_CEIS_Msk
12943#define RNG_SR_SEIS_Pos (6U)
12944#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
12945#define RNG_SR_SEIS RNG_SR_SEIS_Msk
12946
12947/******************************************************************************/
12948/* */
12949/* Real-Time Clock (RTC) */
12950/* */
12951/******************************************************************************/
12952
12953/******************** Bits definition for RTC_TR register *******************/
12954#define RTC_TR_PM_Pos (22U)
12955#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
12956#define RTC_TR_PM RTC_TR_PM_Msk
12957#define RTC_TR_HT_Pos (20U)
12958#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
12959#define RTC_TR_HT RTC_TR_HT_Msk
12960#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
12961#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
12962#define RTC_TR_HU_Pos (16U)
12963#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
12964#define RTC_TR_HU RTC_TR_HU_Msk
12965#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
12966#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
12967#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
12968#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
12969#define RTC_TR_MNT_Pos (12U)
12970#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
12971#define RTC_TR_MNT RTC_TR_MNT_Msk
12972#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
12973#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
12974#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
12975#define RTC_TR_MNU_Pos (8U)
12976#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
12977#define RTC_TR_MNU RTC_TR_MNU_Msk
12978#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
12979#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
12980#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
12981#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
12982#define RTC_TR_ST_Pos (4U)
12983#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
12984#define RTC_TR_ST RTC_TR_ST_Msk
12985#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
12986#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
12987#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
12988#define RTC_TR_SU_Pos (0U)
12989#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
12990#define RTC_TR_SU RTC_TR_SU_Msk
12991#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
12992#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
12993#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
12994#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
12996/******************** Bits definition for RTC_DR register *******************/
12997#define RTC_DR_YT_Pos (20U)
12998#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
12999#define RTC_DR_YT RTC_DR_YT_Msk
13000#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
13001#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
13002#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
13003#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
13004#define RTC_DR_YU_Pos (16U)
13005#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
13006#define RTC_DR_YU RTC_DR_YU_Msk
13007#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
13008#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
13009#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
13010#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
13011#define RTC_DR_WDU_Pos (13U)
13012#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
13013#define RTC_DR_WDU RTC_DR_WDU_Msk
13014#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
13015#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
13016#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
13017#define RTC_DR_MT_Pos (12U)
13018#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
13019#define RTC_DR_MT RTC_DR_MT_Msk
13020#define RTC_DR_MU_Pos (8U)
13021#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
13022#define RTC_DR_MU RTC_DR_MU_Msk
13023#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
13024#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
13025#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
13026#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
13027#define RTC_DR_DT_Pos (4U)
13028#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
13029#define RTC_DR_DT RTC_DR_DT_Msk
13030#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
13031#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
13032#define RTC_DR_DU_Pos (0U)
13033#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
13034#define RTC_DR_DU RTC_DR_DU_Msk
13035#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
13036#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
13037#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
13038#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
13040/******************** Bits definition for RTC_SSR register ******************/
13041#define RTC_SSR_SS_Pos (0U)
13042#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
13043#define RTC_SSR_SS RTC_SSR_SS_Msk
13044
13045/******************** Bits definition for RTC_ICSR register ******************/
13046#define RTC_ICSR_RECALPF_Pos (16U)
13047#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos)
13048#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
13049#define RTC_ICSR_INIT_Pos (7U)
13050#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos)
13051#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
13052#define RTC_ICSR_INITF_Pos (6U)
13053#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos)
13054#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
13055#define RTC_ICSR_RSF_Pos (5U)
13056#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos)
13057#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
13058#define RTC_ICSR_INITS_Pos (4U)
13059#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos)
13060#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
13061#define RTC_ICSR_SHPF_Pos (3U)
13062#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos)
13063#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
13064#define RTC_ICSR_WUTWF_Pos (2U)
13065#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos)
13066#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
13067#define RTC_ICSR_ALRBWF_Pos (1U)
13068#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos)
13069#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
13070#define RTC_ICSR_ALRAWF_Pos (0U)
13071#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos)
13072#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
13073
13074/******************** Bits definition for RTC_PRER register *****************/
13075#define RTC_PRER_PREDIV_A_Pos (16U)
13076#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
13077#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
13078#define RTC_PRER_PREDIV_S_Pos (0U)
13079#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
13080#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
13081
13082/******************** Bits definition for RTC_WUTR register *****************/
13083#define RTC_WUTR_WUT_Pos (0U)
13084#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
13085#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
13086
13087/******************** Bits definition for RTC_CR register *******************/
13088#define RTC_CR_OUT2EN_Pos (31U)
13089#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos)
13090#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk
13091#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
13092#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)
13093#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk
13094#define RTC_CR_TAMPALRM_PU_Pos (29U)
13095#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos)
13096#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk
13097#define RTC_CR_TAMPOE_Pos (26U)
13098#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos)
13099#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk
13100#define RTC_CR_TAMPTS_Pos (25U)
13101#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos)
13102#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk
13103#define RTC_CR_ITSE_Pos (24U)
13104#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
13105#define RTC_CR_ITSE RTC_CR_ITSE_Msk
13106#define RTC_CR_COE_Pos (23U)
13107#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
13108#define RTC_CR_COE RTC_CR_COE_Msk
13109#define RTC_CR_OSEL_Pos (21U)
13110#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
13111#define RTC_CR_OSEL RTC_CR_OSEL_Msk
13112#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
13113#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
13114#define RTC_CR_POL_Pos (20U)
13115#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
13116#define RTC_CR_POL RTC_CR_POL_Msk
13117#define RTC_CR_COSEL_Pos (19U)
13118#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
13119#define RTC_CR_COSEL RTC_CR_COSEL_Msk
13120#define RTC_CR_BKP_Pos (18U)
13121#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
13122#define RTC_CR_BKP RTC_CR_BKP_Msk
13123#define RTC_CR_SUB1H_Pos (17U)
13124#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
13125#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
13126#define RTC_CR_ADD1H_Pos (16U)
13127#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
13128#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
13129#define RTC_CR_TSIE_Pos (15U)
13130#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
13131#define RTC_CR_TSIE RTC_CR_TSIE_Msk
13132#define RTC_CR_WUTIE_Pos (14U)
13133#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
13134#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
13135#define RTC_CR_ALRBIE_Pos (13U)
13136#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
13137#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
13138#define RTC_CR_ALRAIE_Pos (12U)
13139#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
13140#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
13141#define RTC_CR_TSE_Pos (11U)
13142#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
13143#define RTC_CR_TSE RTC_CR_TSE_Msk
13144#define RTC_CR_WUTE_Pos (10U)
13145#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
13146#define RTC_CR_WUTE RTC_CR_WUTE_Msk
13147#define RTC_CR_ALRBE_Pos (9U)
13148#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
13149#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
13150#define RTC_CR_ALRAE_Pos (8U)
13151#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
13152#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
13153#define RTC_CR_FMT_Pos (6U)
13154#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
13155#define RTC_CR_FMT RTC_CR_FMT_Msk
13156#define RTC_CR_BYPSHAD_Pos (5U)
13157#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
13158#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
13159#define RTC_CR_REFCKON_Pos (4U)
13160#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
13161#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
13162#define RTC_CR_TSEDGE_Pos (3U)
13163#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
13164#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
13165#define RTC_CR_WUCKSEL_Pos (0U)
13166#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
13167#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
13168#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
13169#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
13170#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
13172/******************** Bits definition for RTC_WPR register ******************/
13173#define RTC_WPR_KEY_Pos (0U)
13174#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
13175#define RTC_WPR_KEY RTC_WPR_KEY_Msk
13176
13177/******************** Bits definition for RTC_CALR register *****************/
13178#define RTC_CALR_CALP_Pos (15U)
13179#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
13180#define RTC_CALR_CALP RTC_CALR_CALP_Msk
13181#define RTC_CALR_CALW8_Pos (14U)
13182#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
13183#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
13184#define RTC_CALR_CALW16_Pos (13U)
13185#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
13186#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
13187#define RTC_CALR_CALM_Pos (0U)
13188#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
13189#define RTC_CALR_CALM RTC_CALR_CALM_Msk
13190#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
13191#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
13192#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
13193#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
13194#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
13195#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
13196#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
13197#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
13198#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
13200/******************** Bits definition for RTC_SHIFTR register ***************/
13201#define RTC_SHIFTR_SUBFS_Pos (0U)
13202#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
13203#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
13204#define RTC_SHIFTR_ADD1S_Pos (31U)
13205#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
13206#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
13207
13208/******************** Bits definition for RTC_TSTR register *****************/
13209#define RTC_TSTR_PM_Pos (22U)
13210#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
13211#define RTC_TSTR_PM RTC_TSTR_PM_Msk
13212#define RTC_TSTR_HT_Pos (20U)
13213#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
13214#define RTC_TSTR_HT RTC_TSTR_HT_Msk
13215#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
13216#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
13217#define RTC_TSTR_HU_Pos (16U)
13218#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
13219#define RTC_TSTR_HU RTC_TSTR_HU_Msk
13220#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
13221#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
13222#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
13223#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
13224#define RTC_TSTR_MNT_Pos (12U)
13225#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
13226#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
13227#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
13228#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
13229#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
13230#define RTC_TSTR_MNU_Pos (8U)
13231#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
13232#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
13233#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
13234#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
13235#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
13236#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
13237#define RTC_TSTR_ST_Pos (4U)
13238#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
13239#define RTC_TSTR_ST RTC_TSTR_ST_Msk
13240#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
13241#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
13242#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
13243#define RTC_TSTR_SU_Pos (0U)
13244#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
13245#define RTC_TSTR_SU RTC_TSTR_SU_Msk
13246#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
13247#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
13248#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
13249#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
13251/******************** Bits definition for RTC_TSDR register *****************/
13252#define RTC_TSDR_WDU_Pos (13U)
13253#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
13254#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
13255#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
13256#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
13257#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
13258#define RTC_TSDR_MT_Pos (12U)
13259#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
13260#define RTC_TSDR_MT RTC_TSDR_MT_Msk
13261#define RTC_TSDR_MU_Pos (8U)
13262#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
13263#define RTC_TSDR_MU RTC_TSDR_MU_Msk
13264#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
13265#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
13266#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
13267#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
13268#define RTC_TSDR_DT_Pos (4U)
13269#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
13270#define RTC_TSDR_DT RTC_TSDR_DT_Msk
13271#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
13272#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
13273#define RTC_TSDR_DU_Pos (0U)
13274#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
13275#define RTC_TSDR_DU RTC_TSDR_DU_Msk
13276#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
13277#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
13278#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
13279#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
13281/******************** Bits definition for RTC_TSSSR register ****************/
13282#define RTC_TSSSR_SS_Pos (0U)
13283#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
13284#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
13285
13286/******************** Bits definition for RTC_ALRMAR register ***************/
13287#define RTC_ALRMAR_MSK4_Pos (31U)
13288#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
13289#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
13290#define RTC_ALRMAR_WDSEL_Pos (30U)
13291#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
13292#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
13293#define RTC_ALRMAR_DT_Pos (28U)
13294#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
13295#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
13296#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
13297#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
13298#define RTC_ALRMAR_DU_Pos (24U)
13299#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
13300#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
13301#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
13302#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
13303#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
13304#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
13305#define RTC_ALRMAR_MSK3_Pos (23U)
13306#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
13307#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
13308#define RTC_ALRMAR_PM_Pos (22U)
13309#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
13310#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
13311#define RTC_ALRMAR_HT_Pos (20U)
13312#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
13313#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
13314#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
13315#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
13316#define RTC_ALRMAR_HU_Pos (16U)
13317#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
13318#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
13319#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
13320#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
13321#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
13322#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
13323#define RTC_ALRMAR_MSK2_Pos (15U)
13324#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
13325#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
13326#define RTC_ALRMAR_MNT_Pos (12U)
13327#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
13328#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
13329#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
13330#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
13331#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
13332#define RTC_ALRMAR_MNU_Pos (8U)
13333#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
13334#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
13335#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
13336#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
13337#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
13338#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
13339#define RTC_ALRMAR_MSK1_Pos (7U)
13340#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
13341#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
13342#define RTC_ALRMAR_ST_Pos (4U)
13343#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
13344#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
13345#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
13346#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
13347#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
13348#define RTC_ALRMAR_SU_Pos (0U)
13349#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
13350#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
13351#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
13352#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
13353#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
13354#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
13356/******************** Bits definition for RTC_ALRMASSR register *************/
13357#define RTC_ALRMASSR_MASKSS_Pos (24U)
13358#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
13359#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
13360#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
13361#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
13362#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
13363#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
13364#define RTC_ALRMASSR_SS_Pos (0U)
13365#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
13366#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
13367
13368/******************** Bits definition for RTC_ALRMBR register ***************/
13369#define RTC_ALRMBR_MSK4_Pos (31U)
13370#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
13371#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
13372#define RTC_ALRMBR_WDSEL_Pos (30U)
13373#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
13374#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
13375#define RTC_ALRMBR_DT_Pos (28U)
13376#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
13377#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
13378#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
13379#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
13380#define RTC_ALRMBR_DU_Pos (24U)
13381#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
13382#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
13383#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
13384#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
13385#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
13386#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
13387#define RTC_ALRMBR_MSK3_Pos (23U)
13388#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
13389#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
13390#define RTC_ALRMBR_PM_Pos (22U)
13391#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
13392#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
13393#define RTC_ALRMBR_HT_Pos (20U)
13394#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
13395#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
13396#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
13397#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
13398#define RTC_ALRMBR_HU_Pos (16U)
13399#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
13400#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
13401#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
13402#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
13403#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
13404#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
13405#define RTC_ALRMBR_MSK2_Pos (15U)
13406#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
13407#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
13408#define RTC_ALRMBR_MNT_Pos (12U)
13409#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
13410#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
13411#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
13412#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
13413#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
13414#define RTC_ALRMBR_MNU_Pos (8U)
13415#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
13416#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
13417#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
13418#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
13419#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
13420#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
13421#define RTC_ALRMBR_MSK1_Pos (7U)
13422#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
13423#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
13424#define RTC_ALRMBR_ST_Pos (4U)
13425#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
13426#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
13427#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
13428#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
13429#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
13430#define RTC_ALRMBR_SU_Pos (0U)
13431#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
13432#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
13433#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
13434#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
13435#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
13436#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
13438/******************** Bits definition for RTC_ALRMASSR register *************/
13439#define RTC_ALRMBSSR_MASKSS_Pos (24U)
13440#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
13441#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
13442#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
13443#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
13444#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
13445#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
13446#define RTC_ALRMBSSR_SS_Pos (0U)
13447#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
13448#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
13449
13450/******************** Bits definition for RTC_SR register *******************/
13451#define RTC_SR_ITSF_Pos (5U)
13452#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos)
13453#define RTC_SR_ITSF RTC_SR_ITSF_Msk
13454#define RTC_SR_TSOVF_Pos (4U)
13455#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos)
13456#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
13457#define RTC_SR_TSF_Pos (3U)
13458#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos)
13459#define RTC_SR_TSF RTC_SR_TSF_Msk
13460#define RTC_SR_WUTF_Pos (2U)
13461#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos)
13462#define RTC_SR_WUTF RTC_SR_WUTF_Msk
13463#define RTC_SR_ALRBF_Pos (1U)
13464#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos)
13465#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
13466#define RTC_SR_ALRAF_Pos (0U)
13467#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos)
13468#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
13469
13470/******************** Bits definition for RTC_MISR register *****************/
13471#define RTC_MISR_ITSMF_Pos (5U)
13472#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos)
13473#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
13474#define RTC_MISR_TSOVMF_Pos (4U)
13475#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos)
13476#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
13477#define RTC_MISR_TSMF_Pos (3U)
13478#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos)
13479#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
13480#define RTC_MISR_WUTMF_Pos (2U)
13481#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos)
13482#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
13483#define RTC_MISR_ALRBMF_Pos (1U)
13484#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos)
13485#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
13486#define RTC_MISR_ALRAMF_Pos (0U)
13487#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos)
13488#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
13489
13490/******************** Bits definition for RTC_SCR register ******************/
13491#define RTC_SCR_CITSF_Pos (5U)
13492#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos)
13493#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
13494#define RTC_SCR_CTSOVF_Pos (4U)
13495#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos)
13496#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
13497#define RTC_SCR_CTSF_Pos (3U)
13498#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos)
13499#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
13500#define RTC_SCR_CWUTF_Pos (2U)
13501#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos)
13502#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
13503#define RTC_SCR_CALRBF_Pos (1U)
13504#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos)
13505#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
13506#define RTC_SCR_CALRAF_Pos (0U)
13507#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos)
13508#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
13509
13510/******************************************************************************/
13511/* */
13512/* Tamper and backup register (TAMP) */
13513/* */
13514/******************************************************************************/
13515/******************** Bits definition for TAMP_CR1 register *****************/
13516#define TAMP_CR1_TAMP1E_Pos (0U)
13517#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos)
13518#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
13519#define TAMP_CR1_TAMP2E_Pos (1U)
13520#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos)
13521#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
13522#define TAMP_CR1_TAMP3E_Pos (2U)
13523#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos)
13524#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
13525#define TAMP_CR1_ITAMP3E_Pos (18U)
13526#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos)
13527#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
13528#define TAMP_CR1_ITAMP4E_Pos (19U)
13529#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos)
13530#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
13531#define TAMP_CR1_ITAMP5E_Pos (20U)
13532#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos)
13533#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
13534#define TAMP_CR1_ITAMP6E_Pos (21U)
13535#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos)
13536#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
13537
13538/******************** Bits definition for TAMP_CR2 register *****************/
13539#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
13540#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)
13541#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
13542#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
13543#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)
13544#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
13545#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
13546#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)
13547#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
13548#define TAMP_CR2_TAMP1MF_Pos (16U)
13549#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos)
13550#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
13551#define TAMP_CR2_TAMP2MF_Pos (17U)
13552#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos)
13553#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
13554#define TAMP_CR2_TAMP3MF_Pos (18U)
13555#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos)
13556#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
13557#define TAMP_CR2_TAMP1TRG_Pos (24U)
13558#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos)
13559#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
13560#define TAMP_CR2_TAMP2TRG_Pos (25U)
13561#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos)
13562#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
13563#define TAMP_CR2_TAMP3TRG_Pos (26U)
13564#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos)
13565#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
13566
13567/******************** Bits definition for TAMP_FLTCR register ***************/
13568#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
13569#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
13570#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
13571#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
13572#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)
13573#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
13574#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
13575#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
13576#define TAMP_FLTCR_TAMPFLT_Pos (3U)
13577#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)
13578#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
13579#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
13580#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
13581#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
13582#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)
13583#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
13584#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
13585#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)
13586#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
13587
13588/******************** Bits definition for TAMP_IER register *****************/
13589#define TAMP_IER_TAMP1IE_Pos (0U)
13590#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos)
13591#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
13592#define TAMP_IER_TAMP2IE_Pos (1U)
13593#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos)
13594#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
13595#define TAMP_IER_TAMP3IE_Pos (2U)
13596#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos)
13597#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
13598#define TAMP_IER_ITAMP3IE_Pos (18U)
13599#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos)
13600#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
13601#define TAMP_IER_ITAMP4IE_Pos (19U)
13602#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos)
13603#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
13604#define TAMP_IER_ITAMP5IE_Pos (20U)
13605#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos)
13606#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
13607#define TAMP_IER_ITAMP6IE_Pos (21U)
13608#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos)
13609#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
13610
13611/******************** Bits definition for TAMP_SR register ******************/
13612#define TAMP_SR_TAMP1F_Pos (0U)
13613#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos)
13614#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
13615#define TAMP_SR_TAMP2F_Pos (1U)
13616#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos)
13617#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
13618#define TAMP_SR_TAMP3F_Pos (2U)
13619#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos)
13620#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
13621#define TAMP_SR_ITAMP3F_Pos (18U)
13622#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos)
13623#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
13624#define TAMP_SR_ITAMP4F_Pos (19U)
13625#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos)
13626#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
13627#define TAMP_SR_ITAMP5F_Pos (20U)
13628#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos)
13629#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
13630#define TAMP_SR_ITAMP6F_Pos (21U)
13631#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos)
13632#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
13633
13634/******************** Bits definition for TAMP_MISR register ****************/
13635#define TAMP_MISR_TAMP1MF_Pos (0U)
13636#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos)
13637#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
13638#define TAMP_MISR_TAMP2MF_Pos (1U)
13639#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos)
13640#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
13641#define TAMP_MISR_TAMP3MF_Pos (2U)
13642#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos)
13643#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
13644#define TAMP_MISR_ITAMP3MF_Pos (18U)
13645#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos)
13646#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
13647#define TAMP_MISR_ITAMP4MF_Pos (19U)
13648#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos)
13649#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
13650#define TAMP_MISR_ITAMP5MF_Pos (20U)
13651#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos)
13652#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
13653#define TAMP_MISR_ITAMP6MF_Pos (21U)
13654#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos)
13655#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
13656
13657/******************** Bits definition for TAMP_SCR register *****************/
13658#define TAMP_SCR_CTAMP1F_Pos (0U)
13659#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos)
13660#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
13661#define TAMP_SCR_CTAMP2F_Pos (1U)
13662#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos)
13663#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
13664#define TAMP_SCR_CTAMP3F_Pos (2U)
13665#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos)
13666#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
13667#define TAMP_SCR_CITAMP3F_Pos (18U)
13668#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos)
13669#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
13670#define TAMP_SCR_CITAMP4F_Pos (19U)
13671#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos)
13672#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
13673#define TAMP_SCR_CITAMP5F_Pos (20U)
13674#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos)
13675#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
13676#define TAMP_SCR_CITAMP6F_Pos (21U)
13677#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos)
13678#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
13679
13680/******************** Bits definition for TAMP_BKP0R register ***************/
13681#define TAMP_BKP0R_Pos (0U)
13682#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos)
13683#define TAMP_BKP0R TAMP_BKP0R_Msk
13684
13685/******************** Bits definition for TAMP_BKP1R register ***************/
13686#define TAMP_BKP1R_Pos (0U)
13687#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos)
13688#define TAMP_BKP1R TAMP_BKP1R_Msk
13689
13690/******************** Bits definition for TAMP_BKP2R register ***************/
13691#define TAMP_BKP2R_Pos (0U)
13692#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos)
13693#define TAMP_BKP2R TAMP_BKP2R_Msk
13694
13695/******************** Bits definition for TAMP_BKP3R register ***************/
13696#define TAMP_BKP3R_Pos (0U)
13697#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos)
13698#define TAMP_BKP3R TAMP_BKP3R_Msk
13699
13700/******************** Bits definition for TAMP_BKP4R register ***************/
13701#define TAMP_BKP4R_Pos (0U)
13702#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos)
13703#define TAMP_BKP4R TAMP_BKP4R_Msk
13704
13705/******************** Bits definition for TAMP_BKP5R register ***************/
13706#define TAMP_BKP5R_Pos (0U)
13707#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos)
13708#define TAMP_BKP5R TAMP_BKP5R_Msk
13709
13710/******************** Bits definition for TAMP_BKP6R register ***************/
13711#define TAMP_BKP6R_Pos (0U)
13712#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos)
13713#define TAMP_BKP6R TAMP_BKP6R_Msk
13714
13715/******************** Bits definition for TAMP_BKP7R register ***************/
13716#define TAMP_BKP7R_Pos (0U)
13717#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos)
13718#define TAMP_BKP7R TAMP_BKP7R_Msk
13719
13720/******************** Bits definition for TAMP_BKP8R register ***************/
13721#define TAMP_BKP8R_Pos (0U)
13722#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos)
13723#define TAMP_BKP8R TAMP_BKP8R_Msk
13724
13725/******************** Bits definition for TAMP_BKP9R register ***************/
13726#define TAMP_BKP9R_Pos (0U)
13727#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos)
13728#define TAMP_BKP9R TAMP_BKP9R_Msk
13729
13730/******************** Bits definition for TAMP_BKP10R register ***************/
13731#define TAMP_BKP10R_Pos (0U)
13732#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos)
13733#define TAMP_BKP10R TAMP_BKP10R_Msk
13734
13735/******************** Bits definition for TAMP_BKP11R register ***************/
13736#define TAMP_BKP11R_Pos (0U)
13737#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos)
13738#define TAMP_BKP11R TAMP_BKP11R_Msk
13739
13740/******************** Bits definition for TAMP_BKP12R register ***************/
13741#define TAMP_BKP12R_Pos (0U)
13742#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos)
13743#define TAMP_BKP12R TAMP_BKP12R_Msk
13744
13745/******************** Bits definition for TAMP_BKP13R register ***************/
13746#define TAMP_BKP13R_Pos (0U)
13747#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos)
13748#define TAMP_BKP13R TAMP_BKP13R_Msk
13749
13750/******************** Bits definition for TAMP_BKP14R register ***************/
13751#define TAMP_BKP14R_Pos (0U)
13752#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos)
13753#define TAMP_BKP14R TAMP_BKP14R_Msk
13754
13755/******************** Bits definition for TAMP_BKP15R register ***************/
13756#define TAMP_BKP15R_Pos (0U)
13757#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos)
13758#define TAMP_BKP15R TAMP_BKP15R_Msk
13759
13760/******************** Bits definition for TAMP_BKP16R register ***************/
13761#define TAMP_BKP16R_Pos (0U)
13762#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos)
13763#define TAMP_BKP16R TAMP_BKP16R_Msk
13764
13765/******************** Bits definition for TAMP_BKP17R register ***************/
13766#define TAMP_BKP17R_Pos (0U)
13767#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos)
13768#define TAMP_BKP17R TAMP_BKP17R_Msk
13769
13770/******************** Bits definition for TAMP_BKP18R register ***************/
13771#define TAMP_BKP18R_Pos (0U)
13772#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos)
13773#define TAMP_BKP18R TAMP_BKP18R_Msk
13774
13775/******************** Bits definition for TAMP_BKP19R register ***************/
13776#define TAMP_BKP19R_Pos (0U)
13777#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos)
13778#define TAMP_BKP19R TAMP_BKP19R_Msk
13779
13780/******************** Bits definition for TAMP_BKP20R register ***************/
13781#define TAMP_BKP20R_Pos (0U)
13782#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos)
13783#define TAMP_BKP20R TAMP_BKP20R_Msk
13784
13785/******************** Bits definition for TAMP_BKP21R register ***************/
13786#define TAMP_BKP21R_Pos (0U)
13787#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos)
13788#define TAMP_BKP21R TAMP_BKP21R_Msk
13789
13790/******************** Bits definition for TAMP_BKP22R register ***************/
13791#define TAMP_BKP22R_Pos (0U)
13792#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos)
13793#define TAMP_BKP22R TAMP_BKP22R_Msk
13794
13795/******************** Bits definition for TAMP_BKP23R register ***************/
13796#define TAMP_BKP23R_Pos (0U)
13797#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos)
13798#define TAMP_BKP23R TAMP_BKP23R_Msk
13799
13800/******************** Bits definition for TAMP_BKP24R register ***************/
13801#define TAMP_BKP24R_Pos (0U)
13802#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos)
13803#define TAMP_BKP24R TAMP_BKP24R_Msk
13804
13805/******************** Bits definition for TAMP_BKP25R register ***************/
13806#define TAMP_BKP25R_Pos (0U)
13807#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos)
13808#define TAMP_BKP25R TAMP_BKP25R_Msk
13809
13810/******************** Bits definition for TAMP_BKP26R register ***************/
13811#define TAMP_BKP26R_Pos (0U)
13812#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos)
13813#define TAMP_BKP26R TAMP_BKP26R_Msk
13814
13815/******************** Bits definition for TAMP_BKP27R register ***************/
13816#define TAMP_BKP27R_Pos (0U)
13817#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos)
13818#define TAMP_BKP27R TAMP_BKP27R_Msk
13819
13820/******************** Bits definition for TAMP_BKP28R register ***************/
13821#define TAMP_BKP28R_Pos (0U)
13822#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos)
13823#define TAMP_BKP28R TAMP_BKP28R_Msk
13824
13825/******************** Bits definition for TAMP_BKP29R register ***************/
13826#define TAMP_BKP29R_Pos (0U)
13827#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos)
13828#define TAMP_BKP29R TAMP_BKP29R_Msk
13829
13830/******************** Bits definition for TAMP_BKP30R register ***************/
13831#define TAMP_BKP30R_Pos (0U)
13832#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos)
13833#define TAMP_BKP30R TAMP_BKP30R_Msk
13834
13835/******************** Bits definition for TAMP_BKP31R register ***************/
13836#define TAMP_BKP31R_Pos (0U)
13837#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos)
13838#define TAMP_BKP31R TAMP_BKP31R_Msk
13839
13840
13841/******************************************************************************/
13842/* */
13843/* Serial Audio Interface */
13844/* */
13845/******************************************************************************/
13846/******************** Bit definition for SAI_GCR register *******************/
13847#define SAI_GCR_SYNCIN_Pos (0U)
13848#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
13849#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
13850#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
13851#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
13853#define SAI_GCR_SYNCOUT_Pos (4U)
13854#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
13855#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
13856#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
13857#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
13859/******************* Bit definition for SAI_xCR1 register *******************/
13860#define SAI_xCR1_MODE_Pos (0U)
13861#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
13862#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
13863#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
13864#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
13866#define SAI_xCR1_PRTCFG_Pos (2U)
13867#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
13868#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
13869#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
13870#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
13872#define SAI_xCR1_DS_Pos (5U)
13873#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
13874#define SAI_xCR1_DS SAI_xCR1_DS_Msk
13875#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
13876#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
13877#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
13879#define SAI_xCR1_LSBFIRST_Pos (8U)
13880#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
13881#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
13882#define SAI_xCR1_CKSTR_Pos (9U)
13883#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
13884#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
13886#define SAI_xCR1_SYNCEN_Pos (10U)
13887#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
13888#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
13889#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
13890#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
13892#define SAI_xCR1_MONO_Pos (12U)
13893#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
13894#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
13895#define SAI_xCR1_OUTDRIV_Pos (13U)
13896#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
13897#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
13898#define SAI_xCR1_SAIEN_Pos (16U)
13899#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
13900#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
13901#define SAI_xCR1_DMAEN_Pos (17U)
13902#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
13903#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
13904#define SAI_xCR1_NODIV_Pos (19U)
13905#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
13906#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
13908#define SAI_xCR1_MCKDIV_Pos (20U)
13909#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)
13910#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
13911#define SAI_xCR1_MCKDIV_0 (0x00100000U)
13912#define SAI_xCR1_MCKDIV_1 (0x00200000U)
13913#define SAI_xCR1_MCKDIV_2 (0x00400000U)
13914#define SAI_xCR1_MCKDIV_3 (0x00800000U)
13915#define SAI_xCR1_MCKDIV_4 (0x01000000U)
13916#define SAI_xCR1_MCKDIV_5 (0x02000000U)
13918#define SAI_xCR1_OSR_Pos (26U)
13919#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)
13920#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk
13922#define SAI_xCR1_MCKEN_Pos (27U)
13923#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)
13924#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk
13926/******************* Bit definition for SAI_xCR2 register *******************/
13927#define SAI_xCR2_FTH_Pos (0U)
13928#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
13929#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
13930#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
13931#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
13932#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
13934#define SAI_xCR2_FFLUSH_Pos (3U)
13935#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
13936#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
13937#define SAI_xCR2_TRIS_Pos (4U)
13938#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
13939#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
13940#define SAI_xCR2_MUTE_Pos (5U)
13941#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
13942#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
13943#define SAI_xCR2_MUTEVAL_Pos (6U)
13944#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
13945#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
13948#define SAI_xCR2_MUTECNT_Pos (7U)
13949#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
13950#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
13951#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
13952#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
13953#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
13954#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
13955#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
13956#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
13958#define SAI_xCR2_CPL_Pos (13U)
13959#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
13960#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
13961#define SAI_xCR2_COMP_Pos (14U)
13962#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
13963#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
13964#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
13965#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
13968/****************** Bit definition for SAI_xFRCR register *******************/
13969#define SAI_xFRCR_FRL_Pos (0U)
13970#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
13971#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
13972#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
13973#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
13974#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
13975#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
13976#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
13977#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
13978#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
13979#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
13981#define SAI_xFRCR_FSALL_Pos (8U)
13982#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
13983#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
13984#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
13985#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
13986#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
13987#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
13988#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
13989#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
13990#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
13992#define SAI_xFRCR_FSDEF_Pos (16U)
13993#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
13994#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
13995#define SAI_xFRCR_FSPOL_Pos (17U)
13996#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
13997#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
13998#define SAI_xFRCR_FSOFF_Pos (18U)
13999#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
14000#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
14002/****************** Bit definition for SAI_xSLOTR register *******************/
14003#define SAI_xSLOTR_FBOFF_Pos (0U)
14004#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
14005#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
14006#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
14007#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
14008#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
14009#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
14010#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
14012#define SAI_xSLOTR_SLOTSZ_Pos (6U)
14013#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
14014#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
14015#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
14016#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
14018#define SAI_xSLOTR_NBSLOT_Pos (8U)
14019#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
14020#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
14021#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
14022#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
14023#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
14024#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
14026#define SAI_xSLOTR_SLOTEN_Pos (16U)
14027#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
14028#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
14030/******************* Bit definition for SAI_xIMR register *******************/
14031#define SAI_xIMR_OVRUDRIE_Pos (0U)
14032#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
14033#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
14034#define SAI_xIMR_MUTEDETIE_Pos (1U)
14035#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
14036#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
14037#define SAI_xIMR_WCKCFGIE_Pos (2U)
14038#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
14039#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
14040#define SAI_xIMR_FREQIE_Pos (3U)
14041#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
14042#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
14043#define SAI_xIMR_CNRDYIE_Pos (4U)
14044#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
14045#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
14046#define SAI_xIMR_AFSDETIE_Pos (5U)
14047#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
14048#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
14049#define SAI_xIMR_LFSDETIE_Pos (6U)
14050#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
14051#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
14053/******************** Bit definition for SAI_xSR register *******************/
14054#define SAI_xSR_OVRUDR_Pos (0U)
14055#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
14056#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
14057#define SAI_xSR_MUTEDET_Pos (1U)
14058#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
14059#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
14060#define SAI_xSR_WCKCFG_Pos (2U)
14061#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
14062#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
14063#define SAI_xSR_FREQ_Pos (3U)
14064#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
14065#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
14066#define SAI_xSR_CNRDY_Pos (4U)
14067#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
14068#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
14069#define SAI_xSR_AFSDET_Pos (5U)
14070#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
14071#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
14072#define SAI_xSR_LFSDET_Pos (6U)
14073#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
14074#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
14076#define SAI_xSR_FLVL_Pos (16U)
14077#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
14078#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
14079#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
14080#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
14081#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
14083/****************** Bit definition for SAI_xCLRFR register ******************/
14084#define SAI_xCLRFR_COVRUDR_Pos (0U)
14085#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
14086#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
14087#define SAI_xCLRFR_CMUTEDET_Pos (1U)
14088#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
14089#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
14090#define SAI_xCLRFR_CWCKCFG_Pos (2U)
14091#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
14092#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
14093#define SAI_xCLRFR_CFREQ_Pos (3U)
14094#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
14095#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
14096#define SAI_xCLRFR_CCNRDY_Pos (4U)
14097#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
14098#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
14099#define SAI_xCLRFR_CAFSDET_Pos (5U)
14100#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
14101#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
14102#define SAI_xCLRFR_CLFSDET_Pos (6U)
14103#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
14104#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
14106/****************** Bit definition for SAI_xDR register ******************/
14107#define SAI_xDR_DATA_Pos (0U)
14108#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
14109#define SAI_xDR_DATA SAI_xDR_DATA_Msk
14110
14111/****************** Bit definition for SAI_PDMCR register *******************/
14112#define SAI_PDMCR_PDMEN_Pos (0U)
14113#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)
14114#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk
14116#define SAI_PDMCR_MICNBR_Pos (4U)
14117#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)
14118#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk
14119#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)
14120#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)
14122#define SAI_PDMCR_CKEN1_Pos (8U)
14123#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)
14124#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk
14125#define SAI_PDMCR_CKEN2_Pos (9U)
14126#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)
14127#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk
14128#define SAI_PDMCR_CKEN3_Pos (10U)
14129#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)
14130#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk
14131#define SAI_PDMCR_CKEN4_Pos (11U)
14132#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)
14133#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk
14135/****************** Bit definition for SAI_PDMDLY register ******************/
14136#define SAI_PDMDLY_DLYM1L_Pos (0U)
14137#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)
14138#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk
14139#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)
14140#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)
14141#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)
14143#define SAI_PDMDLY_DLYM1R_Pos (4U)
14144#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)
14145#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk
14146#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)
14147#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)
14148#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)
14150#define SAI_PDMDLY_DLYM2L_Pos (8U)
14151#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)
14152#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk
14153#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)
14154#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)
14155#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)
14157#define SAI_PDMDLY_DLYM2R_Pos (12U)
14158#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)
14159#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk
14160#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)
14161#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)
14162#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)
14164#define SAI_PDMDLY_DLYM3L_Pos (16U)
14165#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)
14166#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk
14167#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)
14168#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)
14169#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)
14171#define SAI_PDMDLY_DLYM3R_Pos (20U)
14172#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)
14173#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk
14174#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)
14175#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)
14176#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)
14178#define SAI_PDMDLY_DLYM4L_Pos (24U)
14179#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)
14180#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk
14181#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)
14182#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)
14183#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)
14185#define SAI_PDMDLY_DLYM4R_Pos (28U)
14186#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)
14187#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk
14188#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)
14189#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)
14190#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)
14193/******************************************************************************/
14194/* */
14195/* Serial Peripheral Interface (SPI) */
14196/* */
14197/******************************************************************************/
14198/*
14199 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
14200 */
14201#define SPI_I2S_SUPPORT
14203/******************* Bit definition for SPI_CR1 register ********************/
14204#define SPI_CR1_CPHA_Pos (0U)
14205#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
14206#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
14207#define SPI_CR1_CPOL_Pos (1U)
14208#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
14209#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
14210#define SPI_CR1_MSTR_Pos (2U)
14211#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
14212#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
14214#define SPI_CR1_BR_Pos (3U)
14215#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
14216#define SPI_CR1_BR SPI_CR1_BR_Msk
14217#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
14218#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
14219#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
14221#define SPI_CR1_SPE_Pos (6U)
14222#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
14223#define SPI_CR1_SPE SPI_CR1_SPE_Msk
14224#define SPI_CR1_LSBFIRST_Pos (7U)
14225#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
14226#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
14227#define SPI_CR1_SSI_Pos (8U)
14228#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
14229#define SPI_CR1_SSI SPI_CR1_SSI_Msk
14230#define SPI_CR1_SSM_Pos (9U)
14231#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
14232#define SPI_CR1_SSM SPI_CR1_SSM_Msk
14233#define SPI_CR1_RXONLY_Pos (10U)
14234#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
14235#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
14236#define SPI_CR1_CRCL_Pos (11U)
14237#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
14238#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
14239#define SPI_CR1_CRCNEXT_Pos (12U)
14240#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
14241#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
14242#define SPI_CR1_CRCEN_Pos (13U)
14243#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
14244#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
14245#define SPI_CR1_BIDIOE_Pos (14U)
14246#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
14247#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
14248#define SPI_CR1_BIDIMODE_Pos (15U)
14249#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
14250#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
14252/******************* Bit definition for SPI_CR2 register ********************/
14253#define SPI_CR2_RXDMAEN_Pos (0U)
14254#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
14255#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
14256#define SPI_CR2_TXDMAEN_Pos (1U)
14257#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
14258#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
14259#define SPI_CR2_SSOE_Pos (2U)
14260#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
14261#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
14262#define SPI_CR2_NSSP_Pos (3U)
14263#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
14264#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
14265#define SPI_CR2_FRF_Pos (4U)
14266#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
14267#define SPI_CR2_FRF SPI_CR2_FRF_Msk
14268#define SPI_CR2_ERRIE_Pos (5U)
14269#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
14270#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
14271#define SPI_CR2_RXNEIE_Pos (6U)
14272#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
14273#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
14274#define SPI_CR2_TXEIE_Pos (7U)
14275#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
14276#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
14277#define SPI_CR2_DS_Pos (8U)
14278#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
14279#define SPI_CR2_DS SPI_CR2_DS_Msk
14280#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
14281#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
14282#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
14283#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
14284#define SPI_CR2_FRXTH_Pos (12U)
14285#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
14286#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
14287#define SPI_CR2_LDMARX_Pos (13U)
14288#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
14289#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
14290#define SPI_CR2_LDMATX_Pos (14U)
14291#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
14292#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
14294/******************** Bit definition for SPI_SR register ********************/
14295#define SPI_SR_RXNE_Pos (0U)
14296#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
14297#define SPI_SR_RXNE SPI_SR_RXNE_Msk
14298#define SPI_SR_TXE_Pos (1U)
14299#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
14300#define SPI_SR_TXE SPI_SR_TXE_Msk
14301#define SPI_SR_CHSIDE_Pos (2U)
14302#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
14303#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
14304#define SPI_SR_UDR_Pos (3U)
14305#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
14306#define SPI_SR_UDR SPI_SR_UDR_Msk
14307#define SPI_SR_CRCERR_Pos (4U)
14308#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
14309#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
14310#define SPI_SR_MODF_Pos (5U)
14311#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
14312#define SPI_SR_MODF SPI_SR_MODF_Msk
14313#define SPI_SR_OVR_Pos (6U)
14314#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
14315#define SPI_SR_OVR SPI_SR_OVR_Msk
14316#define SPI_SR_BSY_Pos (7U)
14317#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
14318#define SPI_SR_BSY SPI_SR_BSY_Msk
14319#define SPI_SR_FRE_Pos (8U)
14320#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
14321#define SPI_SR_FRE SPI_SR_FRE_Msk
14322#define SPI_SR_FRLVL_Pos (9U)
14323#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
14324#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
14325#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
14326#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
14327#define SPI_SR_FTLVL_Pos (11U)
14328#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
14329#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
14330#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
14331#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
14333/******************** Bit definition for SPI_DR register ********************/
14334#define SPI_DR_DR_Pos (0U)
14335#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
14336#define SPI_DR_DR SPI_DR_DR_Msk
14338/******************* Bit definition for SPI_CRCPR register ******************/
14339#define SPI_CRCPR_CRCPOLY_Pos (0U)
14340#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
14341#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
14343/****************** Bit definition for SPI_RXCRCR register ******************/
14344#define SPI_RXCRCR_RXCRC_Pos (0U)
14345#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
14346#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
14348/****************** Bit definition for SPI_TXCRCR register ******************/
14349#define SPI_TXCRCR_TXCRC_Pos (0U)
14350#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
14351#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
14353/****************** Bit definition for SPI_I2SCFGR register *****************/
14354#define SPI_I2SCFGR_CHLEN_Pos (0U)
14355#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
14356#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
14357#define SPI_I2SCFGR_DATLEN_Pos (1U)
14358#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
14359#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
14360#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
14361#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
14362#define SPI_I2SCFGR_CKPOL_Pos (3U)
14363#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
14364#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
14365#define SPI_I2SCFGR_I2SSTD_Pos (4U)
14366#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
14367#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
14368#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
14369#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
14370#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
14371#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
14372#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
14373#define SPI_I2SCFGR_I2SCFG_Pos (8U)
14374#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
14375#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
14376#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
14377#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
14378#define SPI_I2SCFGR_I2SE_Pos (10U)
14379#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
14380#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
14381#define SPI_I2SCFGR_I2SMOD_Pos (11U)
14382#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
14383#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
14384#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
14385#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
14386#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
14388/****************** Bit definition for SPI_I2SPR register *******************/
14389#define SPI_I2SPR_I2SDIV_Pos (0U)
14390#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
14391#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
14392#define SPI_I2SPR_ODD_Pos (8U)
14393#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
14394#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
14395#define SPI_I2SPR_MCKOE_Pos (9U)
14396#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
14397#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
14399/******************************************************************************/
14400/* */
14401/* SYSCFG */
14402/* */
14403/******************************************************************************/
14404/****************** Bit definition for SYSCFG_MEMRMP register ***************/
14405#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
14406#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
14407#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
14408#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
14409#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
14410#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
14412#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
14413#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)
14414#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk
14416/****************** Bit definition for SYSCFG_CFGR1 register ******************/
14417#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
14418#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)
14419#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk
14420#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
14421#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)
14422#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk
14423#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
14424#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)
14425#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk
14426#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
14427#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)
14428#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk
14429#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
14430#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)
14431#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk
14432#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
14433#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)
14434#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk
14435#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
14436#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)
14437#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk
14438#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
14439#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)
14440#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk
14441#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
14442#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)
14443#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk
14444#define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
14445#define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos)
14446#define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk
14447#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U)
14448#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U)
14449#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U)
14450#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U)
14451#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U)
14452#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U)
14454/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
14455#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
14456#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)
14457#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
14458#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
14459#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)
14460#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
14461#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
14462#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)
14463#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
14464#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
14465#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)
14466#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
14471#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)
14472#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
14473#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
14474#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
14475#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)
14476#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
14477#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)
14482#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)
14483#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
14484#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
14485#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
14486#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)
14487#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
14488#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)
14493#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)
14494#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
14495#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
14496#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
14497#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)
14498#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
14499#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)
14504#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)
14505#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
14506#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
14507#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
14508#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)
14509#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)
14510#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)
14512/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
14513#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
14514#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)
14515#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
14516#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
14517#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)
14518#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
14519#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
14520#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)
14521#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
14522#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
14523#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)
14524#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
14529#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)
14530#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
14531#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
14532#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
14533#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)
14534#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
14535#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)
14540#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)
14541#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
14542#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
14543#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
14544#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)
14545#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
14546#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)
14551#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)
14552#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
14553#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
14554#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
14555#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)
14556#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
14557#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)
14562#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)
14563#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
14564#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
14565#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
14566#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)
14567#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)
14568#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)
14570/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
14571#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
14572#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)
14573#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
14574#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
14575#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)
14576#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
14577#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
14578#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)
14579#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
14580#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
14581#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)
14582#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
14587#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)
14588#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
14589#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
14590#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
14591#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
14592#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)
14593#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)
14598#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)
14599#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
14600#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
14601#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
14602#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)
14603#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
14604#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)
14609#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)
14610#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
14611#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
14612#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
14613#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)
14614#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
14619#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)
14620#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
14621#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
14622#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
14623#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)
14624#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)
14626/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
14627#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
14628#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)
14629#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
14630#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
14631#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)
14632#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
14633#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
14634#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)
14635#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
14636#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
14637#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)
14638#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
14643#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)
14644#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
14645#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
14646#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
14647#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
14648#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)
14653#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)
14654#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
14655#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
14656#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
14657#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
14658#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)
14663#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)
14664#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
14665#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
14666#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
14667#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
14668#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)
14673#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)
14674#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
14675#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
14676#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
14677#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)
14678#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)
14680/****************** Bit definition for SYSCFG_SCSR register ****************/
14681#define SYSCFG_SCSR_CCMER_Pos (0U)
14682#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos)
14683#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk
14684#define SYSCFG_SCSR_CCMBSY_Pos (1U)
14685#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)
14686#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk
14688/****************** Bit definition for SYSCFG_CFGR2 register ****************/
14689#define SYSCFG_CFGR2_CLL_Pos (0U)
14690#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)
14691#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk
14692#define SYSCFG_CFGR2_SPL_Pos (1U)
14693#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)
14694#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk
14695#define SYSCFG_CFGR2_PVDL_Pos (2U)
14696#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos)
14697#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk
14698#define SYSCFG_CFGR2_ECCL_Pos (3U)
14699#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)
14700#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk
14701#define SYSCFG_CFGR2_SPF_Pos (8U)
14702#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)
14703#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk
14705/****************** Bit definition for SYSCFG_SWPR register ****************/
14706#define SYSCFG_SWPR_PAGE0_Pos (0U)
14707#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos)
14708#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk)
14709#define SYSCFG_SWPR_PAGE1_Pos (1U)
14710#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos)
14711#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk)
14712#define SYSCFG_SWPR_PAGE2_Pos (2U)
14713#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos)
14714#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk)
14715#define SYSCFG_SWPR_PAGE3_Pos (3U)
14716#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos)
14717#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk)
14718#define SYSCFG_SWPR_PAGE4_Pos (4U)
14719#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos)
14720#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk)
14721#define SYSCFG_SWPR_PAGE5_Pos (5U)
14722#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos)
14723#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk)
14724#define SYSCFG_SWPR_PAGE6_Pos (6U)
14725#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos)
14726#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk)
14727#define SYSCFG_SWPR_PAGE7_Pos (7U)
14728#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos)
14729#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk)
14730#define SYSCFG_SWPR_PAGE8_Pos (8U)
14731#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos)
14732#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk)
14733#define SYSCFG_SWPR_PAGE9_Pos (9U)
14734#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos)
14735#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk)
14736#define SYSCFG_SWPR_PAGE10_Pos (10U)
14737#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos)
14738#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk)
14739#define SYSCFG_SWPR_PAGE11_Pos (11U)
14740#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos)
14741#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk)
14742#define SYSCFG_SWPR_PAGE12_Pos (12U)
14743#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos)
14744#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk)
14745#define SYSCFG_SWPR_PAGE13_Pos (13U)
14746#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos)
14747#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk)
14748#define SYSCFG_SWPR_PAGE14_Pos (14U)
14749#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos)
14750#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk)
14751#define SYSCFG_SWPR_PAGE15_Pos (15U)
14752#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos)
14753#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk)
14754#define SYSCFG_SWPR_PAGE16_Pos (16U)
14755#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos)
14756#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk)
14757#define SYSCFG_SWPR_PAGE17_Pos (17U)
14758#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos)
14759#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk)
14760#define SYSCFG_SWPR_PAGE18_Pos (18U)
14761#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos)
14762#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk)
14763#define SYSCFG_SWPR_PAGE19_Pos (19U)
14764#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos)
14765#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk)
14766#define SYSCFG_SWPR_PAGE20_Pos (20U)
14767#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos)
14768#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk)
14769#define SYSCFG_SWPR_PAGE21_Pos (21U)
14770#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos)
14771#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk)
14772#define SYSCFG_SWPR_PAGE22_Pos (22U)
14773#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos)
14774#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk)
14775#define SYSCFG_SWPR_PAGE23_Pos (23U)
14776#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos)
14777#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk)
14778#define SYSCFG_SWPR_PAGE24_Pos (24U)
14779#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos)
14780#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk)
14781#define SYSCFG_SWPR_PAGE25_Pos (25U)
14782#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos)
14783#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk)
14784#define SYSCFG_SWPR_PAGE26_Pos (26U)
14785#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos)
14786#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk)
14787#define SYSCFG_SWPR_PAGE27_Pos (27U)
14788#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos)
14789#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk)
14790#define SYSCFG_SWPR_PAGE28_Pos (28U)
14791#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos)
14792#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk)
14793#define SYSCFG_SWPR_PAGE29_Pos (29U)
14794#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos)
14795#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk)
14796#define SYSCFG_SWPR_PAGE30_Pos (30U)
14797#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos)
14798#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk)
14799#define SYSCFG_SWPR_PAGE31_Pos (31U)
14800#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos)
14801#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk)
14803/****************** Bit definition for SYSCFG_SKR register ****************/
14804#define SYSCFG_SKR_KEY_Pos (0U)
14805#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos)
14806#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk
14808/******************************************************************************/
14809/* */
14810/* TIM */
14811/* */
14812/******************************************************************************/
14813/******************* Bit definition for TIM_CR1 register ********************/
14814#define TIM_CR1_CEN_Pos (0U)
14815#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
14816#define TIM_CR1_CEN TIM_CR1_CEN_Msk
14817#define TIM_CR1_UDIS_Pos (1U)
14818#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
14819#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
14820#define TIM_CR1_URS_Pos (2U)
14821#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
14822#define TIM_CR1_URS TIM_CR1_URS_Msk
14823#define TIM_CR1_OPM_Pos (3U)
14824#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
14825#define TIM_CR1_OPM TIM_CR1_OPM_Msk
14826#define TIM_CR1_DIR_Pos (4U)
14827#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
14828#define TIM_CR1_DIR TIM_CR1_DIR_Msk
14830#define TIM_CR1_CMS_Pos (5U)
14831#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
14832#define TIM_CR1_CMS TIM_CR1_CMS_Msk
14833#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
14834#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
14836#define TIM_CR1_ARPE_Pos (7U)
14837#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
14838#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
14840#define TIM_CR1_CKD_Pos (8U)
14841#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
14842#define TIM_CR1_CKD TIM_CR1_CKD_Msk
14843#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
14844#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
14846#define TIM_CR1_UIFREMAP_Pos (11U)
14847#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
14848#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
14850#define TIM_CR1_DITHEN_Pos (12U)
14851#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos)
14852#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk
14854/******************* Bit definition for TIM_CR2 register ********************/
14855#define TIM_CR2_CCPC_Pos (0U)
14856#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
14857#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
14858#define TIM_CR2_CCUS_Pos (2U)
14859#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
14860#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
14861#define TIM_CR2_CCDS_Pos (3U)
14862#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
14863#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
14865#define TIM_CR2_MMS_Pos (4U)
14866#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos)
14867#define TIM_CR2_MMS TIM_CR2_MMS_Msk
14868#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos)
14869#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos)
14870#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos)
14871#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos)
14873#define TIM_CR2_TI1S_Pos (7U)
14874#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
14875#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
14876#define TIM_CR2_OIS1_Pos (8U)
14877#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
14878#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
14879#define TIM_CR2_OIS1N_Pos (9U)
14880#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
14881#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
14882#define TIM_CR2_OIS2_Pos (10U)
14883#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
14884#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
14885#define TIM_CR2_OIS2N_Pos (11U)
14886#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
14887#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
14888#define TIM_CR2_OIS3_Pos (12U)
14889#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
14890#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
14891#define TIM_CR2_OIS3N_Pos (13U)
14892#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
14893#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
14894#define TIM_CR2_OIS4_Pos (14U)
14895#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
14896#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
14897#define TIM_CR2_OIS4N_Pos (15U)
14898#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos)
14899#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk
14900#define TIM_CR2_OIS5_Pos (16U)
14901#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
14902#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
14903#define TIM_CR2_OIS6_Pos (18U)
14904#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
14905#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
14907#define TIM_CR2_MMS2_Pos (20U)
14908#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
14909#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
14910#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
14911#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
14912#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
14913#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
14915/******************* Bit definition for TIM_SMCR register *******************/
14916#define TIM_SMCR_SMS_Pos (0U)
14917#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
14918#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
14919#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
14920#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
14921#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
14922#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
14924#define TIM_SMCR_OCCS_Pos (3U)
14925#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)
14926#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk
14928#define TIM_SMCR_TS_Pos (4U)
14929#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)
14930#define TIM_SMCR_TS TIM_SMCR_TS_Msk
14931#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)
14932#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)
14933#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)
14934#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)
14935#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)
14937#define TIM_SMCR_MSM_Pos (7U)
14938#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
14939#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
14941#define TIM_SMCR_ETF_Pos (8U)
14942#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
14943#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
14944#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
14945#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
14946#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
14947#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
14949#define TIM_SMCR_ETPS_Pos (12U)
14950#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
14951#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
14952#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
14953#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
14955#define TIM_SMCR_ECE_Pos (14U)
14956#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
14957#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
14958#define TIM_SMCR_ETP_Pos (15U)
14959#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
14960#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
14962#define TIM_SMCR_SMSPE_Pos (24U)
14963#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos)
14964#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk
14966#define TIM_SMCR_SMSPS_Pos (25U)
14967#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos)
14968#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk
14970/******************* Bit definition for TIM_DIER register *******************/
14971#define TIM_DIER_UIE_Pos (0U)
14972#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
14973#define TIM_DIER_UIE TIM_DIER_UIE_Msk
14974#define TIM_DIER_CC1IE_Pos (1U)
14975#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
14976#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
14977#define TIM_DIER_CC2IE_Pos (2U)
14978#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
14979#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
14980#define TIM_DIER_CC3IE_Pos (3U)
14981#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
14982#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
14983#define TIM_DIER_CC4IE_Pos (4U)
14984#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
14985#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
14986#define TIM_DIER_COMIE_Pos (5U)
14987#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
14988#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
14989#define TIM_DIER_TIE_Pos (6U)
14990#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
14991#define TIM_DIER_TIE TIM_DIER_TIE_Msk
14992#define TIM_DIER_BIE_Pos (7U)
14993#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
14994#define TIM_DIER_BIE TIM_DIER_BIE_Msk
14995#define TIM_DIER_UDE_Pos (8U)
14996#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
14997#define TIM_DIER_UDE TIM_DIER_UDE_Msk
14998#define TIM_DIER_CC1DE_Pos (9U)
14999#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
15000#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
15001#define TIM_DIER_CC2DE_Pos (10U)
15002#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
15003#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
15004#define TIM_DIER_CC3DE_Pos (11U)
15005#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
15006#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
15007#define TIM_DIER_CC4DE_Pos (12U)
15008#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
15009#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
15010#define TIM_DIER_COMDE_Pos (13U)
15011#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
15012#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
15013#define TIM_DIER_TDE_Pos (14U)
15014#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
15015#define TIM_DIER_TDE TIM_DIER_TDE_Msk
15016#define TIM_DIER_IDXIE_Pos (20U)
15017#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos)
15018#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk
15019#define TIM_DIER_DIRIE_Pos (21U)
15020#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos)
15021#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk
15022#define TIM_DIER_IERRIE_Pos (22U)
15023#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos)
15024#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk
15025#define TIM_DIER_TERRIE_Pos (23U)
15026#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos)
15027#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk
15029/******************** Bit definition for TIM_SR register ********************/
15030#define TIM_SR_UIF_Pos (0U)
15031#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
15032#define TIM_SR_UIF TIM_SR_UIF_Msk
15033#define TIM_SR_CC1IF_Pos (1U)
15034#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
15035#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
15036#define TIM_SR_CC2IF_Pos (2U)
15037#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
15038#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
15039#define TIM_SR_CC3IF_Pos (3U)
15040#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
15041#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
15042#define TIM_SR_CC4IF_Pos (4U)
15043#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
15044#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
15045#define TIM_SR_COMIF_Pos (5U)
15046#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
15047#define TIM_SR_COMIF TIM_SR_COMIF_Msk
15048#define TIM_SR_TIF_Pos (6U)
15049#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
15050#define TIM_SR_TIF TIM_SR_TIF_Msk
15051#define TIM_SR_BIF_Pos (7U)
15052#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
15053#define TIM_SR_BIF TIM_SR_BIF_Msk
15054#define TIM_SR_B2IF_Pos (8U)
15055#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
15056#define TIM_SR_B2IF TIM_SR_B2IF_Msk
15057#define TIM_SR_CC1OF_Pos (9U)
15058#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
15059#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
15060#define TIM_SR_CC2OF_Pos (10U)
15061#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
15062#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
15063#define TIM_SR_CC3OF_Pos (11U)
15064#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
15065#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
15066#define TIM_SR_CC4OF_Pos (12U)
15067#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
15068#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
15069#define TIM_SR_SBIF_Pos (13U)
15070#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
15071#define TIM_SR_SBIF TIM_SR_SBIF_Msk
15072#define TIM_SR_CC5IF_Pos (16U)
15073#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
15074#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
15075#define TIM_SR_CC6IF_Pos (17U)
15076#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
15077#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
15078#define TIM_SR_IDXF_Pos (20U)
15079#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos)
15080#define TIM_SR_IDXF TIM_SR_IDXF_Msk
15081#define TIM_SR_DIRF_Pos (21U)
15082#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos)
15083#define TIM_SR_DIRF TIM_SR_DIRF_Msk
15084#define TIM_SR_IERRF_Pos (22U)
15085#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos)
15086#define TIM_SR_IERRF TIM_SR_IERRF_Msk
15087#define TIM_SR_TERRF_Pos (23U)
15088#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos)
15089#define TIM_SR_TERRF TIM_SR_TERRF_Msk
15091/******************* Bit definition for TIM_EGR register ********************/
15092#define TIM_EGR_UG_Pos (0U)
15093#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
15094#define TIM_EGR_UG TIM_EGR_UG_Msk
15095#define TIM_EGR_CC1G_Pos (1U)
15096#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
15097#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
15098#define TIM_EGR_CC2G_Pos (2U)
15099#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
15100#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
15101#define TIM_EGR_CC3G_Pos (3U)
15102#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
15103#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
15104#define TIM_EGR_CC4G_Pos (4U)
15105#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
15106#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
15107#define TIM_EGR_COMG_Pos (5U)
15108#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
15109#define TIM_EGR_COMG TIM_EGR_COMG_Msk
15110#define TIM_EGR_TG_Pos (6U)
15111#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
15112#define TIM_EGR_TG TIM_EGR_TG_Msk
15113#define TIM_EGR_BG_Pos (7U)
15114#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
15115#define TIM_EGR_BG TIM_EGR_BG_Msk
15116#define TIM_EGR_B2G_Pos (8U)
15117#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
15118#define TIM_EGR_B2G TIM_EGR_B2G_Msk
15121/****************** Bit definition for TIM_CCMR1 register *******************/
15122#define TIM_CCMR1_CC1S_Pos (0U)
15123#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
15124#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
15125#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
15126#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
15128#define TIM_CCMR1_OC1FE_Pos (2U)
15129#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
15130#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
15131#define TIM_CCMR1_OC1PE_Pos (3U)
15132#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
15133#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
15135#define TIM_CCMR1_OC1M_Pos (4U)
15136#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
15137#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
15138#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
15139#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
15140#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
15141#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
15143#define TIM_CCMR1_OC1CE_Pos (7U)
15144#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
15145#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
15147#define TIM_CCMR1_CC2S_Pos (8U)
15148#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
15149#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
15150#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
15151#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
15153#define TIM_CCMR1_OC2FE_Pos (10U)
15154#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
15155#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
15156#define TIM_CCMR1_OC2PE_Pos (11U)
15157#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
15158#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
15160#define TIM_CCMR1_OC2M_Pos (12U)
15161#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
15162#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
15163#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
15164#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
15165#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
15166#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
15168#define TIM_CCMR1_OC2CE_Pos (15U)
15169#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
15170#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
15172/*----------------------------------------------------------------------------*/
15173#define TIM_CCMR1_IC1PSC_Pos (2U)
15174#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
15175#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
15176#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
15177#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
15179#define TIM_CCMR1_IC1F_Pos (4U)
15180#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
15181#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
15182#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
15183#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
15184#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
15185#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
15187#define TIM_CCMR1_IC2PSC_Pos (10U)
15188#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
15189#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
15190#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
15191#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
15193#define TIM_CCMR1_IC2F_Pos (12U)
15194#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
15195#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
15196#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
15197#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
15198#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
15199#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
15201/****************** Bit definition for TIM_CCMR2 register *******************/
15202#define TIM_CCMR2_CC3S_Pos (0U)
15203#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
15204#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
15205#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
15206#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
15208#define TIM_CCMR2_OC3FE_Pos (2U)
15209#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
15210#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
15211#define TIM_CCMR2_OC3PE_Pos (3U)
15212#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
15213#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
15215#define TIM_CCMR2_OC3M_Pos (4U)
15216#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
15217#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
15218#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
15219#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
15220#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
15221#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
15223#define TIM_CCMR2_OC3CE_Pos (7U)
15224#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
15225#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
15227#define TIM_CCMR2_CC4S_Pos (8U)
15228#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
15229#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
15230#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
15231#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
15233#define TIM_CCMR2_OC4FE_Pos (10U)
15234#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
15235#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
15236#define TIM_CCMR2_OC4PE_Pos (11U)
15237#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
15238#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
15240#define TIM_CCMR2_OC4M_Pos (12U)
15241#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
15242#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
15243#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
15244#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
15245#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
15246#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
15248#define TIM_CCMR2_OC4CE_Pos (15U)
15249#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
15250#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
15252/*----------------------------------------------------------------------------*/
15253#define TIM_CCMR2_IC3PSC_Pos (2U)
15254#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
15255#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
15256#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
15257#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
15259#define TIM_CCMR2_IC3F_Pos (4U)
15260#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
15261#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
15262#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
15263#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
15264#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
15265#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
15267#define TIM_CCMR2_IC4PSC_Pos (10U)
15268#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
15269#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
15270#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
15271#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
15273#define TIM_CCMR2_IC4F_Pos (12U)
15274#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
15275#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
15276#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
15277#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
15278#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
15279#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
15281/****************** Bit definition for TIM_CCMR3 register *******************/
15282#define TIM_CCMR3_OC5FE_Pos (2U)
15283#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
15284#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
15285#define TIM_CCMR3_OC5PE_Pos (3U)
15286#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
15287#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
15289#define TIM_CCMR3_OC5M_Pos (4U)
15290#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
15291#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
15292#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
15293#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
15294#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
15295#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
15297#define TIM_CCMR3_OC5CE_Pos (7U)
15298#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
15299#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
15301#define TIM_CCMR3_OC6FE_Pos (10U)
15302#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
15303#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
15304#define TIM_CCMR3_OC6PE_Pos (11U)
15305#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
15306#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
15308#define TIM_CCMR3_OC6M_Pos (12U)
15309#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
15310#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
15311#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
15312#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
15313#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
15314#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
15316#define TIM_CCMR3_OC6CE_Pos (15U)
15317#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
15318#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
15320/******************* Bit definition for TIM_CCER register *******************/
15321#define TIM_CCER_CC1E_Pos (0U)
15322#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
15323#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
15324#define TIM_CCER_CC1P_Pos (1U)
15325#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
15326#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
15327#define TIM_CCER_CC1NE_Pos (2U)
15328#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
15329#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
15330#define TIM_CCER_CC1NP_Pos (3U)
15331#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
15332#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
15333#define TIM_CCER_CC2E_Pos (4U)
15334#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
15335#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
15336#define TIM_CCER_CC2P_Pos (5U)
15337#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
15338#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
15339#define TIM_CCER_CC2NE_Pos (6U)
15340#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
15341#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
15342#define TIM_CCER_CC2NP_Pos (7U)
15343#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
15344#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
15345#define TIM_CCER_CC3E_Pos (8U)
15346#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
15347#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
15348#define TIM_CCER_CC3P_Pos (9U)
15349#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
15350#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
15351#define TIM_CCER_CC3NE_Pos (10U)
15352#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
15353#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
15354#define TIM_CCER_CC3NP_Pos (11U)
15355#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
15356#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
15357#define TIM_CCER_CC4E_Pos (12U)
15358#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
15359#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
15360#define TIM_CCER_CC4P_Pos (13U)
15361#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
15362#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
15363#define TIM_CCER_CC4NE_Pos (14U)
15364#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos)
15365#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk
15366#define TIM_CCER_CC4NP_Pos (15U)
15367#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
15368#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
15369#define TIM_CCER_CC5E_Pos (16U)
15370#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
15371#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
15372#define TIM_CCER_CC5P_Pos (17U)
15373#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
15374#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
15375#define TIM_CCER_CC6E_Pos (20U)
15376#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
15377#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
15378#define TIM_CCER_CC6P_Pos (21U)
15379#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
15380#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
15382/******************* Bit definition for TIM_CNT register ********************/
15383#define TIM_CNT_CNT_Pos (0U)
15384#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
15385#define TIM_CNT_CNT TIM_CNT_CNT_Msk
15386#define TIM_CNT_UIFCPY_Pos (31U)
15387#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
15388#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
15390/******************* Bit definition for TIM_PSC register ********************/
15391#define TIM_PSC_PSC_Pos (0U)
15392#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
15393#define TIM_PSC_PSC TIM_PSC_PSC_Msk
15395/******************* Bit definition for TIM_ARR register ********************/
15396#define TIM_ARR_ARR_Pos (0U)
15397#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
15398#define TIM_ARR_ARR TIM_ARR_ARR_Msk
15400/******************* Bit definition for TIM_RCR register ********************/
15401#define TIM_RCR_REP_Pos (0U)
15402#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
15403#define TIM_RCR_REP TIM_RCR_REP_Msk
15405/******************* Bit definition for TIM_CCR1 register *******************/
15406#define TIM_CCR1_CCR1_Pos (0U)
15407#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
15408#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
15410/******************* Bit definition for TIM_CCR2 register *******************/
15411#define TIM_CCR2_CCR2_Pos (0U)
15412#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
15413#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
15415/******************* Bit definition for TIM_CCR3 register *******************/
15416#define TIM_CCR3_CCR3_Pos (0U)
15417#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
15418#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
15420/******************* Bit definition for TIM_CCR4 register *******************/
15421#define TIM_CCR4_CCR4_Pos (0U)
15422#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
15423#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
15425/******************* Bit definition for TIM_CCR5 register *******************/
15426#define TIM_CCR5_CCR5_Pos (0U)
15427#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
15428#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
15429#define TIM_CCR5_GC5C1_Pos (29U)
15430#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
15431#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
15432#define TIM_CCR5_GC5C2_Pos (30U)
15433#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
15434#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
15435#define TIM_CCR5_GC5C3_Pos (31U)
15436#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
15437#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
15439/******************* Bit definition for TIM_CCR6 register *******************/
15440#define TIM_CCR6_CCR6_Pos (0U)
15441#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
15442#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
15444/******************* Bit definition for TIM_BDTR register *******************/
15445#define TIM_BDTR_DTG_Pos (0U)
15446#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
15447#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
15448#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
15449#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
15450#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
15451#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
15452#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
15453#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
15454#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
15455#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
15457#define TIM_BDTR_LOCK_Pos (8U)
15458#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
15459#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
15460#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
15461#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
15463#define TIM_BDTR_OSSI_Pos (10U)
15464#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
15465#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
15466#define TIM_BDTR_OSSR_Pos (11U)
15467#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
15468#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
15469#define TIM_BDTR_BKE_Pos (12U)
15470#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
15471#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
15472#define TIM_BDTR_BKP_Pos (13U)
15473#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
15474#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
15475#define TIM_BDTR_AOE_Pos (14U)
15476#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
15477#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
15478#define TIM_BDTR_MOE_Pos (15U)
15479#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
15480#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
15482#define TIM_BDTR_BKF_Pos (16U)
15483#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
15484#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
15485#define TIM_BDTR_BK2F_Pos (20U)
15486#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
15487#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
15489#define TIM_BDTR_BK2E_Pos (24U)
15490#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
15491#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
15492#define TIM_BDTR_BK2P_Pos (25U)
15493#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
15494#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
15496#define TIM_BDTR_BKDSRM_Pos (26U)
15497#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos)
15498#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk
15499#define TIM_BDTR_BK2DSRM_Pos (27U)
15500#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos)
15501#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk
15503#define TIM_BDTR_BKBID_Pos (28U)
15504#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos)
15505#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk
15506#define TIM_BDTR_BK2BID_Pos (29U)
15507#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos)
15508#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk
15510/******************* Bit definition for TIM_DCR register ********************/
15511#define TIM_DCR_DBA_Pos (0U)
15512#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
15513#define TIM_DCR_DBA TIM_DCR_DBA_Msk
15514#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
15515#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
15516#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
15517#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
15518#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
15520#define TIM_DCR_DBL_Pos (8U)
15521#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
15522#define TIM_DCR_DBL TIM_DCR_DBL_Msk
15523#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
15524#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
15525#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
15526#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
15527#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
15529/******************* Bit definition for TIM1_AF1 register *******************/
15530#define TIM1_AF1_BKINE_Pos (0U)
15531#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)
15532#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk
15533#define TIM1_AF1_BKCMP1E_Pos (1U)
15534#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)
15535#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk
15536#define TIM1_AF1_BKCMP2E_Pos (2U)
15537#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)
15538#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk
15539#define TIM1_AF1_BKCMP3E_Pos (3U)
15540#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos)
15541#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk
15542#define TIM1_AF1_BKCMP4E_Pos (4U)
15543#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos)
15544#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk
15545#define TIM1_AF1_BKCMP5E_Pos (5U)
15546#define TIM1_AF1_BKCMP5E_Msk (0x1UL << TIM1_AF1_BKCMP5E_Pos)
15547#define TIM1_AF1_BKCMP5E TIM1_AF1_BKCMP5E_Msk
15548#define TIM1_AF1_BKCMP6E_Pos (6U)
15549#define TIM1_AF1_BKCMP6E_Msk (0x1UL << TIM1_AF1_BKCMP6E_Pos)
15550#define TIM1_AF1_BKCMP6E TIM1_AF1_BKCMP6E_Msk
15551#define TIM1_AF1_BKCMP7E_Pos (7U)
15552#define TIM1_AF1_BKCMP7E_Msk (0x1UL << TIM1_AF1_BKCMP7E_Pos)
15553#define TIM1_AF1_BKCMP7E TIM1_AF1_BKCMP7E_Msk
15554#define TIM1_AF1_BKINP_Pos (9U)
15555#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)
15556#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk
15557#define TIM1_AF1_BKCMP1P_Pos (10U)
15558#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)
15559#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk
15560#define TIM1_AF1_BKCMP2P_Pos (11U)
15561#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)
15562#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk
15563#define TIM1_AF1_BKCMP3P_Pos (12U)
15564#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos)
15565#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk
15566#define TIM1_AF1_BKCMP4P_Pos (13U)
15567#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos)
15568#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk
15569#define TIM1_AF1_ETRSEL_Pos (14U)
15570#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)
15571#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk
15572#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)
15573#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)
15574#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)
15575#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)
15577/******************* Bit definition for TIM1_AF2 register *********************/
15578#define TIM1_AF2_BK2INE_Pos (0U)
15579#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)
15580#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk
15581#define TIM1_AF2_BK2CMP1E_Pos (1U)
15582#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)
15583#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk
15584#define TIM1_AF2_BK2CMP2E_Pos (2U)
15585#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)
15586#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk
15587#define TIM1_AF2_BK2CMP3E_Pos (3U)
15588#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos)
15589#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk
15590#define TIM1_AF2_BK2CMP4E_Pos (4U)
15591#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos)
15592#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk
15593#define TIM1_AF2_BK2CMP5E_Pos (5U)
15594#define TIM1_AF2_BK2CMP5E_Msk (0x1UL << TIM1_AF2_BK2CMP5E_Pos)
15595#define TIM1_AF2_BK2CMP5E TIM1_AF2_BK2CMP5E_Msk
15596#define TIM1_AF2_BK2CMP6E_Pos (6U)
15597#define TIM1_AF2_BK2CMP6E_Msk (0x1UL << TIM1_AF2_BK2CMP6E_Pos)
15598#define TIM1_AF2_BK2CMP6E TIM1_AF2_BK2CMP6E_Msk
15599#define TIM1_AF2_BK2CMP7E_Pos (7U)
15600#define TIM1_AF2_BK2CMP7E_Msk (0x1UL << TIM1_AF2_BK2CMP7E_Pos)
15601#define TIM1_AF2_BK2CMP7E TIM1_AF2_BK2CMP7E_Msk
15602#define TIM1_AF2_BK2INP_Pos (9U)
15603#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)
15604#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk
15605#define TIM1_AF2_BK2CMP1P_Pos (10U)
15606#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)
15607#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk
15608#define TIM1_AF2_BK2CMP2P_Pos (11U)
15609#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)
15610#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk
15611#define TIM1_AF2_BK2CMP3P_Pos (12U)
15612#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos)
15613#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk
15614#define TIM1_AF2_BK2CMP4P_Pos (13U)
15615#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos)
15616#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk
15617#define TIM1_AF2_OCRSEL_Pos (16U)
15618#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos)
15619#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk
15620#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos)
15621#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos)
15622#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos)
15624/******************* Bit definition for TIM_OR register *********************/
15625#define TIM_OR_HSE32EN_Pos (0U)
15626#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos)
15627#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk
15629/******************* Bit definition for TIM_TISEL register *********************/
15630#define TIM_TISEL_TI1SEL_Pos (0U)
15631#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)
15632#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk
15633#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)
15634#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)
15635#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)
15636#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)
15638#define TIM_TISEL_TI2SEL_Pos (8U)
15639#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)
15640#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk
15641#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)
15642#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)
15643#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)
15644#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)
15646#define TIM_TISEL_TI3SEL_Pos (16U)
15647#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)
15648#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk
15649#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)
15650#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)
15651#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)
15652#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)
15654#define TIM_TISEL_TI4SEL_Pos (24U)
15655#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)
15656#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk
15657#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)
15658#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)
15659#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)
15660#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)
15662/******************* Bit definition for TIM_DTR2 register *********************/
15663#define TIM_DTR2_DTGF_Pos (0U)
15664#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos)
15665#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk
15666#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos)
15667#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos)
15668#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos)
15669#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos)
15670#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos)
15671#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos)
15672#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos)
15673#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos)
15675#define TIM_DTR2_DTAE_Pos (16U)
15676#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos)
15677#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk
15678#define TIM_DTR2_DTPE_Pos (17U)
15679#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos)
15680#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk
15682/******************* Bit definition for TIM_ECR register *********************/
15683#define TIM_ECR_IE_Pos (0U)
15684#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos)
15685#define TIM_ECR_IE TIM_ECR_IE_Msk
15687#define TIM_ECR_IDIR_Pos (1U)
15688#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos)
15689#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk
15690#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos)
15691#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos)
15693#define TIM_ECR_FIDX_Pos (5U)
15694#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos)
15695#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk
15697#define TIM_ECR_IPOS_Pos (6U)
15698#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos)
15699#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk
15700#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos)
15701#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos)
15703#define TIM_ECR_PW_Pos (16U)
15704#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos)
15705#define TIM_ECR_PW TIM_ECR_PW_Msk
15706#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos)
15707#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos)
15708#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos)
15709#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos)
15710#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos)
15711#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos)
15712#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos)
15713#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos)
15715#define TIM_ECR_PWPRSC_Pos (24U)
15716#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos)
15717#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk
15718#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos)
15719#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos)
15720#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos)
15722/******************* Bit definition for TIM_DMAR register *******************/
15723#define TIM_DMAR_DMAB_Pos (0U)
15724#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)
15725#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
15727/******************************************************************************/
15728/* */
15729/* Low Power Timer (LPTIM) */
15730/* */
15731/******************************************************************************/
15732/****************** Bit definition for LPTIM_ISR register *******************/
15733#define LPTIM_ISR_CMPM_Pos (0U)
15734#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
15735#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
15736#define LPTIM_ISR_ARRM_Pos (1U)
15737#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
15738#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
15739#define LPTIM_ISR_EXTTRIG_Pos (2U)
15740#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
15741#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
15742#define LPTIM_ISR_CMPOK_Pos (3U)
15743#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
15744#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
15745#define LPTIM_ISR_ARROK_Pos (4U)
15746#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
15747#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
15748#define LPTIM_ISR_UP_Pos (5U)
15749#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
15750#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
15751#define LPTIM_ISR_DOWN_Pos (6U)
15752#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
15753#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
15755/****************** Bit definition for LPTIM_ICR register *******************/
15756#define LPTIM_ICR_CMPMCF_Pos (0U)
15757#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
15758#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
15759#define LPTIM_ICR_ARRMCF_Pos (1U)
15760#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
15761#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
15762#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
15763#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
15764#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
15765#define LPTIM_ICR_CMPOKCF_Pos (3U)
15766#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
15767#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
15768#define LPTIM_ICR_ARROKCF_Pos (4U)
15769#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
15770#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
15771#define LPTIM_ICR_UPCF_Pos (5U)
15772#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
15773#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
15774#define LPTIM_ICR_DOWNCF_Pos (6U)
15775#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
15776#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
15778/****************** Bit definition for LPTIM_IER register ********************/
15779#define LPTIM_IER_CMPMIE_Pos (0U)
15780#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
15781#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
15782#define LPTIM_IER_ARRMIE_Pos (1U)
15783#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
15784#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
15785#define LPTIM_IER_EXTTRIGIE_Pos (2U)
15786#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
15787#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
15788#define LPTIM_IER_CMPOKIE_Pos (3U)
15789#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
15790#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
15791#define LPTIM_IER_ARROKIE_Pos (4U)
15792#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
15793#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
15794#define LPTIM_IER_UPIE_Pos (5U)
15795#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
15796#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
15797#define LPTIM_IER_DOWNIE_Pos (6U)
15798#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
15799#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
15801/****************** Bit definition for LPTIM_CFGR register *******************/
15802#define LPTIM_CFGR_CKSEL_Pos (0U)
15803#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
15804#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
15806#define LPTIM_CFGR_CKPOL_Pos (1U)
15807#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
15808#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
15809#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
15810#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
15812#define LPTIM_CFGR_CKFLT_Pos (3U)
15813#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
15814#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
15815#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
15816#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
15818#define LPTIM_CFGR_TRGFLT_Pos (6U)
15819#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
15820#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
15821#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
15822#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
15824#define LPTIM_CFGR_PRESC_Pos (9U)
15825#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
15826#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
15827#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
15828#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
15829#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
15831#define LPTIM_CFGR_TRIGSEL_Pos (13U)
15832#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)
15833#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
15834#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)
15835#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)
15836#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)
15837#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)
15839#define LPTIM_CFGR_TRIGEN_Pos (17U)
15840#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
15841#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
15842#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
15843#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
15845#define LPTIM_CFGR_TIMOUT_Pos (19U)
15846#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
15847#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
15848#define LPTIM_CFGR_WAVE_Pos (20U)
15849#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
15850#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
15851#define LPTIM_CFGR_WAVPOL_Pos (21U)
15852#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
15853#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
15854#define LPTIM_CFGR_PRELOAD_Pos (22U)
15855#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
15856#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
15857#define LPTIM_CFGR_COUNTMODE_Pos (23U)
15858#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
15859#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
15860#define LPTIM_CFGR_ENC_Pos (24U)
15861#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
15862#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
15864/****************** Bit definition for LPTIM_CR register ********************/
15865#define LPTIM_CR_ENABLE_Pos (0U)
15866#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
15867#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
15868#define LPTIM_CR_SNGSTRT_Pos (1U)
15869#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
15870#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
15871#define LPTIM_CR_CNTSTRT_Pos (2U)
15872#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
15873#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
15874#define LPTIM_CR_COUNTRST_Pos (3U)
15875#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)
15876#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk
15877#define LPTIM_CR_RSTARE_Pos (4U)
15878#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)
15879#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk
15881/****************** Bit definition for LPTIM_CMP register *******************/
15882#define LPTIM_CMP_CMP_Pos (0U)
15883#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
15884#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
15886/****************** Bit definition for LPTIM_ARR register *******************/
15887#define LPTIM_ARR_ARR_Pos (0U)
15888#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
15889#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
15891/****************** Bit definition for LPTIM_CNT register *******************/
15892#define LPTIM_CNT_CNT_Pos (0U)
15893#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
15894#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
15896/****************** Bit definition for LPTIM_OR register *******************/
15897#define LPTIM_OR_IN1_Pos (0U)
15898#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos)
15899#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk
15900#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos)
15901#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos)
15902#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos)
15904#define LPTIM_OR_IN2_Pos (1U)
15905#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos)
15906#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk
15907#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos)
15908#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos)
15909#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos)
15910/******************************************************************************/
15911/* */
15912/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
15913/* */
15914/******************************************************************************/
15915/****************** Bit definition for USART_CR1 register *******************/
15916#define USART_CR1_UE_Pos (0U)
15917#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
15918#define USART_CR1_UE USART_CR1_UE_Msk
15919#define USART_CR1_UESM_Pos (1U)
15920#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
15921#define USART_CR1_UESM USART_CR1_UESM_Msk
15922#define USART_CR1_RE_Pos (2U)
15923#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
15924#define USART_CR1_RE USART_CR1_RE_Msk
15925#define USART_CR1_TE_Pos (3U)
15926#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
15927#define USART_CR1_TE USART_CR1_TE_Msk
15928#define USART_CR1_IDLEIE_Pos (4U)
15929#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
15930#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
15931#define USART_CR1_RXNEIE_Pos (5U)
15932#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
15933#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
15934#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
15935#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk
15936#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk
15937#define USART_CR1_TCIE_Pos (6U)
15938#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
15939#define USART_CR1_TCIE USART_CR1_TCIE_Msk
15940#define USART_CR1_TXEIE_Pos (7U)
15941#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
15942#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
15943#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
15944#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk
15945#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk
15946#define USART_CR1_PEIE_Pos (8U)
15947#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
15948#define USART_CR1_PEIE USART_CR1_PEIE_Msk
15949#define USART_CR1_PS_Pos (9U)
15950#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
15951#define USART_CR1_PS USART_CR1_PS_Msk
15952#define USART_CR1_PCE_Pos (10U)
15953#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
15954#define USART_CR1_PCE USART_CR1_PCE_Msk
15955#define USART_CR1_WAKE_Pos (11U)
15956#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
15957#define USART_CR1_WAKE USART_CR1_WAKE_Msk
15958#define USART_CR1_M_Pos (12U)
15959#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
15960#define USART_CR1_M USART_CR1_M_Msk
15961#define USART_CR1_M0_Pos (12U)
15962#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
15963#define USART_CR1_M0 USART_CR1_M0_Msk
15964#define USART_CR1_MME_Pos (13U)
15965#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
15966#define USART_CR1_MME USART_CR1_MME_Msk
15967#define USART_CR1_CMIE_Pos (14U)
15968#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
15969#define USART_CR1_CMIE USART_CR1_CMIE_Msk
15970#define USART_CR1_OVER8_Pos (15U)
15971#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
15972#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
15973#define USART_CR1_DEDT_Pos (16U)
15974#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
15975#define USART_CR1_DEDT USART_CR1_DEDT_Msk
15976#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
15977#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
15978#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
15979#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
15980#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
15981#define USART_CR1_DEAT_Pos (21U)
15982#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
15983#define USART_CR1_DEAT USART_CR1_DEAT_Msk
15984#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
15985#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
15986#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
15987#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
15988#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
15989#define USART_CR1_RTOIE_Pos (26U)
15990#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
15991#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
15992#define USART_CR1_EOBIE_Pos (27U)
15993#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
15994#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
15995#define USART_CR1_M1_Pos (28U)
15996#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
15997#define USART_CR1_M1 USART_CR1_M1_Msk
15998#define USART_CR1_FIFOEN_Pos (29U)
15999#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)
16000#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk
16001#define USART_CR1_TXFEIE_Pos (30U)
16002#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)
16003#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk
16004#define USART_CR1_RXFFIE_Pos (31U)
16005#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)
16006#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk
16008/****************** Bit definition for USART_CR2 register *******************/
16009#define USART_CR2_SLVEN_Pos (0U)
16010#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)
16011#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk
16012#define USART_CR2_DIS_NSS_Pos (3U)
16013#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)
16014#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk
16015#define USART_CR2_ADDM7_Pos (4U)
16016#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
16017#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
16018#define USART_CR2_LBDL_Pos (5U)
16019#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
16020#define USART_CR2_LBDL USART_CR2_LBDL_Msk
16021#define USART_CR2_LBDIE_Pos (6U)
16022#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
16023#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
16024#define USART_CR2_LBCL_Pos (8U)
16025#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
16026#define USART_CR2_LBCL USART_CR2_LBCL_Msk
16027#define USART_CR2_CPHA_Pos (9U)
16028#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
16029#define USART_CR2_CPHA USART_CR2_CPHA_Msk
16030#define USART_CR2_CPOL_Pos (10U)
16031#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
16032#define USART_CR2_CPOL USART_CR2_CPOL_Msk
16033#define USART_CR2_CLKEN_Pos (11U)
16034#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
16035#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
16036#define USART_CR2_STOP_Pos (12U)
16037#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
16038#define USART_CR2_STOP USART_CR2_STOP_Msk
16039#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
16040#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
16041#define USART_CR2_LINEN_Pos (14U)
16042#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
16043#define USART_CR2_LINEN USART_CR2_LINEN_Msk
16044#define USART_CR2_SWAP_Pos (15U)
16045#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
16046#define USART_CR2_SWAP USART_CR2_SWAP_Msk
16047#define USART_CR2_RXINV_Pos (16U)
16048#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
16049#define USART_CR2_RXINV USART_CR2_RXINV_Msk
16050#define USART_CR2_TXINV_Pos (17U)
16051#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
16052#define USART_CR2_TXINV USART_CR2_TXINV_Msk
16053#define USART_CR2_DATAINV_Pos (18U)
16054#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
16055#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
16056#define USART_CR2_MSBFIRST_Pos (19U)
16057#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
16058#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
16059#define USART_CR2_ABREN_Pos (20U)
16060#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
16061#define USART_CR2_ABREN USART_CR2_ABREN_Msk
16062#define USART_CR2_ABRMODE_Pos (21U)
16063#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
16064#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
16065#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
16066#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
16067#define USART_CR2_RTOEN_Pos (23U)
16068#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
16069#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
16070#define USART_CR2_ADD_Pos (24U)
16071#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
16072#define USART_CR2_ADD USART_CR2_ADD_Msk
16074/****************** Bit definition for USART_CR3 register *******************/
16075#define USART_CR3_EIE_Pos (0U)
16076#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
16077#define USART_CR3_EIE USART_CR3_EIE_Msk
16078#define USART_CR3_IREN_Pos (1U)
16079#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
16080#define USART_CR3_IREN USART_CR3_IREN_Msk
16081#define USART_CR3_IRLP_Pos (2U)
16082#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
16083#define USART_CR3_IRLP USART_CR3_IRLP_Msk
16084#define USART_CR3_HDSEL_Pos (3U)
16085#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
16086#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
16087#define USART_CR3_NACK_Pos (4U)
16088#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
16089#define USART_CR3_NACK USART_CR3_NACK_Msk
16090#define USART_CR3_SCEN_Pos (5U)
16091#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
16092#define USART_CR3_SCEN USART_CR3_SCEN_Msk
16093#define USART_CR3_DMAR_Pos (6U)
16094#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
16095#define USART_CR3_DMAR USART_CR3_DMAR_Msk
16096#define USART_CR3_DMAT_Pos (7U)
16097#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
16098#define USART_CR3_DMAT USART_CR3_DMAT_Msk
16099#define USART_CR3_RTSE_Pos (8U)
16100#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
16101#define USART_CR3_RTSE USART_CR3_RTSE_Msk
16102#define USART_CR3_CTSE_Pos (9U)
16103#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
16104#define USART_CR3_CTSE USART_CR3_CTSE_Msk
16105#define USART_CR3_CTSIE_Pos (10U)
16106#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
16107#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
16108#define USART_CR3_ONEBIT_Pos (11U)
16109#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
16110#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
16111#define USART_CR3_OVRDIS_Pos (12U)
16112#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
16113#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
16114#define USART_CR3_DDRE_Pos (13U)
16115#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
16116#define USART_CR3_DDRE USART_CR3_DDRE_Msk
16117#define USART_CR3_DEM_Pos (14U)
16118#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
16119#define USART_CR3_DEM USART_CR3_DEM_Msk
16120#define USART_CR3_DEP_Pos (15U)
16121#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
16122#define USART_CR3_DEP USART_CR3_DEP_Msk
16123#define USART_CR3_SCARCNT_Pos (17U)
16124#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
16125#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
16126#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
16127#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
16128#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
16129#define USART_CR3_WUS_Pos (20U)
16130#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
16131#define USART_CR3_WUS USART_CR3_WUS_Msk
16132#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
16133#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
16134#define USART_CR3_WUFIE_Pos (22U)
16135#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
16136#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
16137#define USART_CR3_TXFTIE_Pos (23U)
16138#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)
16139#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk
16140#define USART_CR3_TCBGTIE_Pos (24U)
16141#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
16142#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
16143#define USART_CR3_RXFTCFG_Pos (25U)
16144#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)
16145#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk
16146#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)
16147#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)
16148#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)
16149#define USART_CR3_RXFTIE_Pos (28U)
16150#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)
16151#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk
16152#define USART_CR3_TXFTCFG_Pos (29U)
16153#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)
16154#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk
16155#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)
16156#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)
16157#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)
16159/****************** Bit definition for USART_BRR register *******************/
16160#define USART_BRR_LPUART_Pos (0U)
16161#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos)
16162#define USART_BRR_LPUART USART_BRR_LPUART_Msk
16163#define USART_BRR_BRR_Pos (0U)
16164#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos)
16165#define USART_BRR_BRR USART_BRR_BRR_Msk
16167/****************** Bit definition for USART_GTPR register ******************/
16168#define USART_GTPR_PSC_Pos (0U)
16169#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
16170#define USART_GTPR_PSC USART_GTPR_PSC_Msk
16171#define USART_GTPR_GT_Pos (8U)
16172#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
16173#define USART_GTPR_GT USART_GTPR_GT_Msk
16175/******************* Bit definition for USART_RTOR register *****************/
16176#define USART_RTOR_RTO_Pos (0U)
16177#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
16178#define USART_RTOR_RTO USART_RTOR_RTO_Msk
16179#define USART_RTOR_BLEN_Pos (24U)
16180#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
16181#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
16183/******************* Bit definition for USART_RQR register ******************/
16184#define USART_RQR_ABRRQ_Pos (0U)
16185#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
16186#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
16187#define USART_RQR_SBKRQ_Pos (1U)
16188#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
16189#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
16190#define USART_RQR_MMRQ_Pos (2U)
16191#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
16192#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
16193#define USART_RQR_RXFRQ_Pos (3U)
16194#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
16195#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
16196#define USART_RQR_TXFRQ_Pos (4U)
16197#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
16198#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
16200/******************* Bit definition for USART_ISR register ******************/
16201#define USART_ISR_PE_Pos (0U)
16202#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
16203#define USART_ISR_PE USART_ISR_PE_Msk
16204#define USART_ISR_FE_Pos (1U)
16205#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
16206#define USART_ISR_FE USART_ISR_FE_Msk
16207#define USART_ISR_NE_Pos (2U)
16208#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
16209#define USART_ISR_NE USART_ISR_NE_Msk
16210#define USART_ISR_ORE_Pos (3U)
16211#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
16212#define USART_ISR_ORE USART_ISR_ORE_Msk
16213#define USART_ISR_IDLE_Pos (4U)
16214#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
16215#define USART_ISR_IDLE USART_ISR_IDLE_Msk
16216#define USART_ISR_RXNE_Pos (5U)
16217#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
16218#define USART_ISR_RXNE USART_ISR_RXNE_Msk
16219#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
16220#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk
16221#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk
16222#define USART_ISR_TC_Pos (6U)
16223#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
16224#define USART_ISR_TC USART_ISR_TC_Msk
16225#define USART_ISR_TXE_Pos (7U)
16226#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
16227#define USART_ISR_TXE USART_ISR_TXE_Msk
16228#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
16229#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk
16230#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk
16231#define USART_ISR_LBDF_Pos (8U)
16232#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
16233#define USART_ISR_LBDF USART_ISR_LBDF_Msk
16234#define USART_ISR_CTSIF_Pos (9U)
16235#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
16236#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
16237#define USART_ISR_CTS_Pos (10U)
16238#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
16239#define USART_ISR_CTS USART_ISR_CTS_Msk
16240#define USART_ISR_RTOF_Pos (11U)
16241#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
16242#define USART_ISR_RTOF USART_ISR_RTOF_Msk
16243#define USART_ISR_EOBF_Pos (12U)
16244#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
16245#define USART_ISR_EOBF USART_ISR_EOBF_Msk
16246#define USART_ISR_UDR_Pos (13U)
16247#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)
16248#define USART_ISR_UDR USART_ISR_UDR_Msk
16249#define USART_ISR_ABRE_Pos (14U)
16250#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
16251#define USART_ISR_ABRE USART_ISR_ABRE_Msk
16252#define USART_ISR_ABRF_Pos (15U)
16253#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
16254#define USART_ISR_ABRF USART_ISR_ABRF_Msk
16255#define USART_ISR_BUSY_Pos (16U)
16256#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
16257#define USART_ISR_BUSY USART_ISR_BUSY_Msk
16258#define USART_ISR_CMF_Pos (17U)
16259#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
16260#define USART_ISR_CMF USART_ISR_CMF_Msk
16261#define USART_ISR_SBKF_Pos (18U)
16262#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
16263#define USART_ISR_SBKF USART_ISR_SBKF_Msk
16264#define USART_ISR_RWU_Pos (19U)
16265#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
16266#define USART_ISR_RWU USART_ISR_RWU_Msk
16267#define USART_ISR_WUF_Pos (20U)
16268#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
16269#define USART_ISR_WUF USART_ISR_WUF_Msk
16270#define USART_ISR_TEACK_Pos (21U)
16271#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
16272#define USART_ISR_TEACK USART_ISR_TEACK_Msk
16273#define USART_ISR_REACK_Pos (22U)
16274#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
16275#define USART_ISR_REACK USART_ISR_REACK_Msk
16276#define USART_ISR_TXFE_Pos (23U)
16277#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)
16278#define USART_ISR_TXFE USART_ISR_TXFE_Msk
16279#define USART_ISR_RXFF_Pos (24U)
16280#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)
16281#define USART_ISR_RXFF USART_ISR_RXFF_Msk
16282#define USART_ISR_TCBGT_Pos (25U)
16283#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
16284#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
16285#define USART_ISR_RXFT_Pos (26U)
16286#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)
16287#define USART_ISR_RXFT USART_ISR_RXFT_Msk
16288#define USART_ISR_TXFT_Pos (27U)
16289#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)
16290#define USART_ISR_TXFT USART_ISR_TXFT_Msk
16292/******************* Bit definition for USART_ICR register ******************/
16293#define USART_ICR_PECF_Pos (0U)
16294#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
16295#define USART_ICR_PECF USART_ICR_PECF_Msk
16296#define USART_ICR_FECF_Pos (1U)
16297#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
16298#define USART_ICR_FECF USART_ICR_FECF_Msk
16299#define USART_ICR_NECF_Pos (2U)
16300#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
16301#define USART_ICR_NECF USART_ICR_NECF_Msk
16302#define USART_ICR_ORECF_Pos (3U)
16303#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
16304#define USART_ICR_ORECF USART_ICR_ORECF_Msk
16305#define USART_ICR_IDLECF_Pos (4U)
16306#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
16307#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
16308#define USART_ICR_TXFECF_Pos (5U)
16309#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)
16310#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk
16311#define USART_ICR_TCCF_Pos (6U)
16312#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
16313#define USART_ICR_TCCF USART_ICR_TCCF_Msk
16314#define USART_ICR_TCBGTCF_Pos (7U)
16315#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
16316#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
16317#define USART_ICR_LBDCF_Pos (8U)
16318#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
16319#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
16320#define USART_ICR_CTSCF_Pos (9U)
16321#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
16322#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
16323#define USART_ICR_RTOCF_Pos (11U)
16324#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
16325#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
16326#define USART_ICR_EOBCF_Pos (12U)
16327#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
16328#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
16329#define USART_ICR_UDRCF_Pos (13U)
16330#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)
16331#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk
16332#define USART_ICR_CMCF_Pos (17U)
16333#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
16334#define USART_ICR_CMCF USART_ICR_CMCF_Msk
16335#define USART_ICR_WUCF_Pos (20U)
16336#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
16337#define USART_ICR_WUCF USART_ICR_WUCF_Msk
16339/******************* Bit definition for USART_RDR register ******************/
16340#define USART_RDR_RDR_Pos (0U)
16341#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
16342#define USART_RDR_RDR USART_RDR_RDR_Msk
16344/******************* Bit definition for USART_TDR register ******************/
16345#define USART_TDR_TDR_Pos (0U)
16346#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
16347#define USART_TDR_TDR USART_TDR_TDR_Msk
16349/******************* Bit definition for USART_PRESC register ****************/
16350#define USART_PRESC_PRESCALER_Pos (0U)
16351#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)
16352#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk
16353#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)
16354#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)
16355#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)
16356#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)
16358/******************************************************************************/
16359/* */
16360/* VREFBUF */
16361/* */
16362/******************************************************************************/
16363/******************* Bit definition for VREFBUF_CSR register ****************/
16364#define VREFBUF_CSR_ENVR_Pos (0U)
16365#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
16366#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
16367#define VREFBUF_CSR_HIZ_Pos (1U)
16368#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
16369#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
16370#define VREFBUF_CSR_VRR_Pos (3U)
16371#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
16372#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
16373#define VREFBUF_CSR_VRS_Pos (4U)
16374#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos)
16375#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
16376#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos)
16377#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos)
16379/******************* Bit definition for VREFBUF_CCR register ******************/
16380#define VREFBUF_CCR_TRIM_Pos (0U)
16381#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
16382#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
16384/******************************************************************************/
16385/* */
16386/* USB Device FS Endpoint registers */
16387/* */
16388/******************************************************************************/
16389#define USB_EP0R USB_BASE
16390#define USB_EP1R (USB_BASE + 0x0x00000004)
16391#define USB_EP2R (USB_BASE + 0x0x00000008)
16392#define USB_EP3R (USB_BASE + 0x0x0000000C)
16393#define USB_EP4R (USB_BASE + 0x0x00000010)
16394#define USB_EP5R (USB_BASE + 0x0x00000014)
16395#define USB_EP6R (USB_BASE + 0x0x00000018)
16396#define USB_EP7R (USB_BASE + 0x0x0000001C)
16398/* bit positions */
16399#define USB_EP_CTR_RX ((uint16_t)0x8000U)
16400#define USB_EP_DTOG_RX ((uint16_t)0x4000U)
16401#define USB_EPRX_STAT ((uint16_t)0x3000U)
16402#define USB_EP_SETUP ((uint16_t)0x0800U)
16403#define USB_EP_T_FIELD ((uint16_t)0x0600U)
16404#define USB_EP_KIND ((uint16_t)0x0100U)
16405#define USB_EP_CTR_TX ((uint16_t)0x0080U)
16406#define USB_EP_DTOG_TX ((uint16_t)0x0040U)
16407#define USB_EPTX_STAT ((uint16_t)0x0030U)
16408#define USB_EPADDR_FIELD ((uint16_t)0x000FU)
16410/* EndPoint REGister MASK (no toggle fields) */
16411#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
16413#define USB_EP_TYPE_MASK ((uint16_t)0x0600U)
16414#define USB_EP_BULK ((uint16_t)0x0000U)
16415#define USB_EP_CONTROL ((uint16_t)0x0200U)
16416#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U)
16417#define USB_EP_INTERRUPT ((uint16_t)0x0600U)
16418#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
16419
16420#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK)
16422#define USB_EP_TX_DIS ((uint16_t)0x0000U)
16423#define USB_EP_TX_STALL ((uint16_t)0x0010U)
16424#define USB_EP_TX_NAK ((uint16_t)0x0020U)
16425#define USB_EP_TX_VALID ((uint16_t)0x0030U)
16426#define USB_EPTX_DTOG1 ((uint16_t)0x0010U)
16427#define USB_EPTX_DTOG2 ((uint16_t)0x0020U)
16428#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
16430#define USB_EP_RX_DIS ((uint16_t)0x0000U)
16431#define USB_EP_RX_STALL ((uint16_t)0x1000U)
16432#define USB_EP_RX_NAK ((uint16_t)0x2000U)
16433#define USB_EP_RX_VALID ((uint16_t)0x3000U)
16434#define USB_EPRX_DTOG1 ((uint16_t)0x1000U)
16435#define USB_EPRX_DTOG2 ((uint16_t)0x2000U)
16436#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
16437
16438/******************************************************************************/
16439/* */
16440/* USB Device FS General registers */
16441/* */
16442/******************************************************************************/
16443#define USB_CNTR (USB_BASE + 0x00000040U)
16444#define USB_ISTR (USB_BASE + 0x00000044U)
16445#define USB_FNR (USB_BASE + 0x00000048U)
16446#define USB_DADDR (USB_BASE + 0x0000004CU)
16447#define USB_BTABLE (USB_BASE + 0x00000050U)
16448#define USB_LPMCSR (USB_BASE + 0x00000054U)
16449#define USB_BCDR (USB_BASE + 0x00000058U)
16451/****************** Bits definition for USB_CNTR register *******************/
16452#define USB_CNTR_CTRM ((uint16_t)0x8000U)
16453#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U)
16454#define USB_CNTR_ERRM ((uint16_t)0x2000U)
16455#define USB_CNTR_WKUPM ((uint16_t)0x1000U)
16456#define USB_CNTR_SUSPM ((uint16_t)0x0800U)
16457#define USB_CNTR_RESETM ((uint16_t)0x0400U)
16458#define USB_CNTR_SOFM ((uint16_t)0x0200U)
16459#define USB_CNTR_ESOFM ((uint16_t)0x0100U)
16460#define USB_CNTR_L1REQM ((uint16_t)0x0080U)
16461#define USB_CNTR_L1RESUME ((uint16_t)0x0020U)
16462#define USB_CNTR_RESUME ((uint16_t)0x0010U)
16463#define USB_CNTR_FSUSP ((uint16_t)0x0008U)
16464#define USB_CNTR_LPMODE ((uint16_t)0x0004U)
16465#define USB_CNTR_PDWN ((uint16_t)0x0002U)
16466#define USB_CNTR_FRES ((uint16_t)0x0001U)
16468/****************** Bits definition for USB_ISTR register *******************/
16469#define USB_ISTR_EP_ID ((uint16_t)0x000FU)
16470#define USB_ISTR_DIR ((uint16_t)0x0010U)
16471#define USB_ISTR_L1REQ ((uint16_t)0x0080U)
16472#define USB_ISTR_ESOF ((uint16_t)0x0100U)
16473#define USB_ISTR_SOF ((uint16_t)0x0200U)
16474#define USB_ISTR_RESET ((uint16_t)0x0400U)
16475#define USB_ISTR_SUSP ((uint16_t)0x0800U)
16476#define USB_ISTR_WKUP ((uint16_t)0x1000U)
16477#define USB_ISTR_ERR ((uint16_t)0x2000U)
16478#define USB_ISTR_PMAOVR ((uint16_t)0x4000U)
16479#define USB_ISTR_CTR ((uint16_t)0x8000U)
16481#define USB_CLR_L1REQ (~USB_ISTR_L1REQ)
16482#define USB_CLR_ESOF (~USB_ISTR_ESOF)
16483#define USB_CLR_SOF (~USB_ISTR_SOF)
16484#define USB_CLR_RESET (~USB_ISTR_RESET)
16485#define USB_CLR_SUSP (~USB_ISTR_SUSP)
16486#define USB_CLR_WKUP (~USB_ISTR_WKUP)
16487#define USB_CLR_ERR (~USB_ISTR_ERR)
16488#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR)
16489#define USB_CLR_CTR (~USB_ISTR_CTR)
16491/****************** Bits definition for USB_FNR register ********************/
16492#define USB_FNR_FN ((uint16_t)0x07FFU)
16493#define USB_FNR_LSOF ((uint16_t)0x1800U)
16494#define USB_FNR_LCK ((uint16_t)0x2000U)
16495#define USB_FNR_RXDM ((uint16_t)0x4000U)
16496#define USB_FNR_RXDP ((uint16_t)0x8000U)
16498/****************** Bits definition for USB_DADDR register ****************/
16499#define USB_DADDR_ADD ((uint8_t)0x7FU)
16500#define USB_DADDR_ADD0 ((uint8_t)0x01U)
16501#define USB_DADDR_ADD1 ((uint8_t)0x02U)
16502#define USB_DADDR_ADD2 ((uint8_t)0x04U)
16503#define USB_DADDR_ADD3 ((uint8_t)0x08U)
16504#define USB_DADDR_ADD4 ((uint8_t)0x10U)
16505#define USB_DADDR_ADD5 ((uint8_t)0x20U)
16506#define USB_DADDR_ADD6 ((uint8_t)0x40U)
16508#define USB_DADDR_EF ((uint8_t)0x80U)
16510/****************** Bit definition for USB_BTABLE register ******************/
16511#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U)
16513/****************** Bits definition for USB_BCDR register *******************/
16514#define USB_BCDR_BCDEN ((uint16_t)0x0001U)
16515#define USB_BCDR_DCDEN ((uint16_t)0x0002U)
16516#define USB_BCDR_PDEN ((uint16_t)0x0004U)
16517#define USB_BCDR_SDEN ((uint16_t)0x0008U)
16518#define USB_BCDR_DCDET ((uint16_t)0x0010U)
16519#define USB_BCDR_PDET ((uint16_t)0x0020U)
16520#define USB_BCDR_SDET ((uint16_t)0x0040U)
16521#define USB_BCDR_PS2DET ((uint16_t)0x0080U)
16522#define USB_BCDR_DPPU ((uint16_t)0x8000U)
16524/******************* Bit definition for LPMCSR register *********************/
16525#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U)
16526#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U)
16527#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U)
16528#define USB_LPMCSR_BESL ((uint16_t)0x00F0U)
16531/***************** Bit definition for USB_ADDR0_TX register *****************/
16532#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
16533#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)
16534#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk
16536/***************** Bit definition for USB_ADDR1_TX register *****************/
16537#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
16538#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)
16539#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk
16541/***************** Bit definition for USB_ADDR2_TX register *****************/
16542#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
16543#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)
16544#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk
16546/***************** Bit definition for USB_ADDR3_TX register *****************/
16547#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
16548#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)
16549#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk
16551/***************** Bit definition for USB_ADDR4_TX register *****************/
16552#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
16553#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)
16554#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk
16556/***************** Bit definition for USB_ADDR5_TX register *****************/
16557#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
16558#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)
16559#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk
16561/***************** Bit definition for USB_ADDR6_TX register *****************/
16562#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
16563#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)
16564#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk
16566/***************** Bit definition for USB_ADDR7_TX register *****************/
16567#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
16568#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)
16569#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk
16571/*----------------------------------------------------------------------------*/
16572
16573/***************** Bit definition for USB_COUNT0_TX register ****************/
16574#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
16575#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)
16576#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk
16578/***************** Bit definition for USB_COUNT1_TX register ****************/
16579#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
16580#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)
16581#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk
16583/***************** Bit definition for USB_COUNT2_TX register ****************/
16584#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
16585#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)
16586#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk
16588/***************** Bit definition for USB_COUNT3_TX register ****************/
16589#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
16590#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)
16591#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk
16593/***************** Bit definition for USB_COUNT4_TX register ****************/
16594#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
16595#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)
16596#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk
16598/***************** Bit definition for USB_COUNT5_TX register ****************/
16599#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
16600#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)
16601#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk
16603/***************** Bit definition for USB_COUNT6_TX register ****************/
16604#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
16605#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)
16606#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk
16608/***************** Bit definition for USB_COUNT7_TX register ****************/
16609#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
16610#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)
16611#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk
16613/*----------------------------------------------------------------------------*/
16614
16615/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
16616#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU)
16618/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
16619#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U)
16621/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
16622#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU)
16624/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
16625#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U)
16627/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
16628#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU)
16630/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
16631#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U)
16633/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
16634#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU)
16636/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
16637#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U)
16639/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
16640#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU)
16642/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
16643#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U)
16645/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
16646#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU)
16648/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
16649#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U)
16651/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
16652#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU)
16654/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
16655#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U)
16657/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
16658#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU)
16660/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
16661#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U)
16663/*----------------------------------------------------------------------------*/
16664
16665/***************** Bit definition for USB_ADDR0_RX register *****************/
16666#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
16667#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)
16668#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk
16670/***************** Bit definition for USB_ADDR1_RX register *****************/
16671#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
16672#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)
16673#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk
16675/***************** Bit definition for USB_ADDR2_RX register *****************/
16676#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
16677#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)
16678#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk
16680/***************** Bit definition for USB_ADDR3_RX register *****************/
16681#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
16682#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)
16683#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk
16685/***************** Bit definition for USB_ADDR4_RX register *****************/
16686#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
16687#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)
16688#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk
16690/***************** Bit definition for USB_ADDR5_RX register *****************/
16691#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
16692#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)
16693#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk
16695/***************** Bit definition for USB_ADDR6_RX register *****************/
16696#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
16697#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)
16698#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk
16700/***************** Bit definition for USB_ADDR7_RX register *****************/
16701#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
16702#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)
16703#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk
16705/*----------------------------------------------------------------------------*/
16706
16707/***************** Bit definition for USB_COUNT0_RX register ****************/
16708#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
16709#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)
16710#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk
16712#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
16713#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)
16714#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk
16715#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
16716#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
16717#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
16718#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
16719#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
16721#define USB_COUNT0_RX_BLSIZE_Pos (15U)
16722#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)
16723#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk
16725/***************** Bit definition for USB_COUNT1_RX register ****************/
16726#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
16727#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)
16728#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk
16730#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
16731#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)
16732#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk
16733#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
16734#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
16735#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
16736#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
16737#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
16739#define USB_COUNT1_RX_BLSIZE_Pos (15U)
16740#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)
16741#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk
16743/***************** Bit definition for USB_COUNT2_RX register ****************/
16744#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
16745#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)
16746#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk
16748#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
16749#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)
16750#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk
16751#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
16752#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
16753#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
16754#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
16755#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
16757#define USB_COUNT2_RX_BLSIZE_Pos (15U)
16758#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)
16759#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk
16761/***************** Bit definition for USB_COUNT3_RX register ****************/
16762#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
16763#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)
16764#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk
16766#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
16767#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)
16768#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk
16769#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
16770#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
16771#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
16772#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
16773#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
16775#define USB_COUNT3_RX_BLSIZE_Pos (15U)
16776#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)
16777#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk
16779/***************** Bit definition for USB_COUNT4_RX register ****************/
16780#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
16781#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)
16782#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk
16784#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
16785#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)
16786#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk
16787#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
16788#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
16789#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
16790#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
16791#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
16793#define USB_COUNT4_RX_BLSIZE_Pos (15U)
16794#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)
16795#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk
16797/***************** Bit definition for USB_COUNT5_RX register ****************/
16798#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
16799#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)
16800#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk
16802#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
16803#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)
16804#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk
16805#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
16806#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
16807#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
16808#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
16809#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
16811#define USB_COUNT5_RX_BLSIZE_Pos (15U)
16812#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)
16813#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk
16815/***************** Bit definition for USB_COUNT6_RX register ****************/
16816#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
16817#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)
16818#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk
16820#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
16821#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)
16822#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk
16823#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
16824#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
16825#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
16826#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
16827#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
16829#define USB_COUNT6_RX_BLSIZE_Pos (15U)
16830#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)
16831#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk
16833/***************** Bit definition for USB_COUNT7_RX register ****************/
16834#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
16835#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)
16836#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk
16838#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
16839#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)
16840#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk
16841#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
16842#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
16843#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
16844#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
16845#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
16847#define USB_COUNT7_RX_BLSIZE_Pos (15U)
16848#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)
16849#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk
16851/*----------------------------------------------------------------------------*/
16852
16853/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
16854#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU)
16856#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U)
16857#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U)
16858#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U)
16859#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U)
16860#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U)
16861#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U)
16863#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U)
16865/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
16866#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U)
16868#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U)
16869#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U)
16870#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U)
16871#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U)
16872#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U)
16873#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U)
16875#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U)
16877/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
16878#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU)
16880#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U)
16881#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U)
16882#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U)
16883#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U)
16884#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U)
16885#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U)
16887#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U)
16889/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
16890#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U)
16892#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U)
16893#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U)
16894#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U)
16895#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U)
16896#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U)
16897#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U)
16899#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U)
16901/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
16902#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU)
16904#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U)
16905#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U)
16906#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U)
16907#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U)
16908#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U)
16909#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U)
16911#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U)
16913/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
16914#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U)
16916#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U)
16917#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U)
16918#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U)
16919#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U)
16920#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U)
16921#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U)
16923#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U)
16925/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
16926#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU)
16928#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U)
16929#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U)
16930#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U)
16931#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U)
16932#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U)
16933#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U)
16935#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U)
16937/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
16938#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U)
16940#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U)
16941#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U)
16942#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U)
16943#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U)
16944#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U)
16945#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U)
16947#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U)
16949/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
16950#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU)
16952#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U)
16953#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U)
16954#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U)
16955#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U)
16956#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U)
16957#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U)
16959#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U)
16961/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
16962#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U)
16964#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U)
16965#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U)
16966#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U)
16967#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U)
16968#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U)
16969#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U)
16971#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U)
16973/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
16974#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU)
16976#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U)
16977#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U)
16978#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U)
16979#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U)
16980#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U)
16981#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U)
16983#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U)
16985/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
16986#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U)
16988#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U)
16989#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U)
16990#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U)
16991#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U)
16992#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U)
16993#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U)
16995#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U)
16997/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
16998#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU)
17000#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U)
17001#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U)
17002#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U)
17003#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U)
17004#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U)
17005#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U)
17007#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U)
17009/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
17010#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U)
17012#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U)
17013#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U)
17014#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U)
17015#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U)
17016#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U)
17017#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U)
17019#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U)
17021/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
17022#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU)
17024#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U)
17025#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U)
17026#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U)
17027#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U)
17028#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U)
17029#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U)
17031#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U)
17033/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
17034#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U)
17036#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U)
17037#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U)
17038#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U)
17039#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U)
17040#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U)
17041#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U)
17043#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U)
17045/******************************************************************************/
17046/* */
17047/* UCPD */
17048/* */
17049/******************************************************************************/
17050/******************** Bits definition for UCPD_CFG1 register *******************/
17051#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
17052#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos)
17053#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk
17054#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos)
17055#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos)
17056#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos)
17057#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos)
17058#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos)
17059#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos)
17060#define UCPD_CFG1_IFRGAP_Pos (6U)
17061#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos)
17062#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk
17063#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos)
17064#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos)
17065#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos)
17066#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos)
17067#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos)
17068#define UCPD_CFG1_TRANSWIN_Pos (11U)
17069#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)
17070#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk
17071#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos)
17072#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos)
17073#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos)
17074#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos)
17075#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos)
17076#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
17077#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos)
17078#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk
17079#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos)
17080#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos)
17081#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos)
17082#define UCPD_CFG1_RXORDSETEN_Pos (20U)
17083#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)
17084#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk
17085#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)
17086#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)
17087#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)
17088#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)
17089#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)
17090#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)
17091#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)
17092#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)
17093#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)
17094#define UCPD_CFG1_TXDMAEN_Pos (29U)
17095#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos)
17096#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk
17097#define UCPD_CFG1_RXDMAEN_Pos (30U)
17098#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos)
17099#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk
17100#define UCPD_CFG1_UCPDEN_Pos (31U)
17101#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos)
17102#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk
17104/******************** Bits definition for UCPD_CFG2 register *******************/
17105#define UCPD_CFG2_RXFILTDIS_Pos (0U)
17106#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)
17107#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk
17108#define UCPD_CFG2_RXFILT2N3_Pos (1U)
17109#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)
17110#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk
17111#define UCPD_CFG2_FORCECLK_Pos (2U)
17112#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos)
17113#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk
17114#define UCPD_CFG2_WUPEN_Pos (3U)
17115#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos)
17116#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk
17118/******************** Bits definition for UCPD_CR register ********************/
17119#define UCPD_CR_TXMODE_Pos (0U)
17120#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos)
17121#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk
17122#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos)
17123#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos)
17124#define UCPD_CR_TXSEND_Pos (2U)
17125#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos)
17126#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk
17127#define UCPD_CR_TXHRST_Pos (3U)
17128#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos)
17129#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk
17130#define UCPD_CR_RXMODE_Pos (4U)
17131#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos)
17132#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk
17133#define UCPD_CR_PHYRXEN_Pos (5U)
17134#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos)
17135#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk
17136#define UCPD_CR_PHYCCSEL_Pos (6U)
17137#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos)
17138#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk
17139#define UCPD_CR_ANASUBMODE_Pos (7U)
17140#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos)
17141#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk
17142#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos)
17143#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos)
17144#define UCPD_CR_ANAMODE_Pos (9U)
17145#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos)
17146#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk
17147#define UCPD_CR_CCENABLE_Pos (10U)
17148#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos)
17149#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk
17150#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos)
17151#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos)
17152#define UCPD_CR_FRSRXEN_Pos (16U)
17153#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos)
17154#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk
17155#define UCPD_CR_FRSTX_Pos (17U)
17156#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos)
17157#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk
17158#define UCPD_CR_RDCH_Pos (18U)
17159#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos)
17160#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk
17161#define UCPD_CR_CC1TCDIS_Pos (20U)
17162#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos)
17163#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk
17164#define UCPD_CR_CC2TCDIS_Pos (21U)
17165#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos)
17166#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk
17168/******************** Bits definition for UCPD_IMR register *******************/
17169#define UCPD_IMR_TXISIE_Pos (0U)
17170#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos)
17171#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk
17172#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
17173#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)
17174#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk
17175#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
17176#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)
17177#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk
17178#define UCPD_IMR_TXMSGABTIE_Pos (3U)
17179#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)
17180#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk
17181#define UCPD_IMR_HRSTDISCIE_Pos (4U)
17182#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)
17183#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk
17184#define UCPD_IMR_HRSTSENTIE_Pos (5U)
17185#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)
17186#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk
17187#define UCPD_IMR_TXUNDIE_Pos (6U)
17188#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos)
17189#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk
17190#define UCPD_IMR_RXNEIE_Pos (8U)
17191#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos)
17192#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk
17193#define UCPD_IMR_RXORDDETIE_Pos (9U)
17194#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos)
17195#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk
17196#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
17197#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)
17198#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk
17199#define UCPD_IMR_RXOVRIE_Pos (11U)
17200#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos)
17201#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk
17202#define UCPD_IMR_RXMSGENDIE_Pos (12U)
17203#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)
17204#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk
17205#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
17206#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)
17207#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk
17208#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
17209#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)
17210#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk
17211#define UCPD_IMR_FRSEVTIE_Pos (20U)
17212#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos)
17213#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk
17215/******************** Bits definition for UCPD_SR register ********************/
17216#define UCPD_SR_TXIS_Pos (0U)
17217#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos)
17218#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk
17219#define UCPD_SR_TXMSGDISC_Pos (1U)
17220#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos)
17221#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk
17222#define UCPD_SR_TXMSGSENT_Pos (2U)
17223#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos)
17224#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk
17225#define UCPD_SR_TXMSGABT_Pos (3U)
17226#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos)
17227#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk
17228#define UCPD_SR_HRSTDISC_Pos (4U)
17229#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos)
17230#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk
17231#define UCPD_SR_HRSTSENT_Pos (5U)
17232#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos)
17233#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk
17234#define UCPD_SR_TXUND_Pos (6U)
17235#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos)
17236#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk
17237#define UCPD_SR_RXNE_Pos (8U)
17238#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos)
17239#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk
17240#define UCPD_SR_RXORDDET_Pos (9U)
17241#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos)
17242#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk
17243#define UCPD_SR_RXHRSTDET_Pos (10U)
17244#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos)
17245#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk
17246#define UCPD_SR_RXOVR_Pos (11U)
17247#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos)
17248#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk
17249#define UCPD_SR_RXMSGEND_Pos (12U)
17250#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos)
17251#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk
17252#define UCPD_SR_RXERR_Pos (13U)
17253#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos)
17254#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk
17255#define UCPD_SR_TYPECEVT1_Pos (14U)
17256#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos)
17257#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk
17258#define UCPD_SR_TYPECEVT2_Pos (15U)
17259#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos)
17260#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk
17261#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
17262#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)
17263#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk
17264#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)
17265#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)
17266#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
17267#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)
17268#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk
17269#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)
17270#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)
17271#define UCPD_SR_FRSEVT_Pos (20U)
17272#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos)
17273#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk
17275/******************** Bits definition for UCPD_ICR register *******************/
17276#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
17277#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)
17278#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk
17279#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
17280#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)
17281#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk
17282#define UCPD_ICR_TXMSGABTCF_Pos (3U)
17283#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)
17284#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk
17285#define UCPD_ICR_HRSTDISCCF_Pos (4U)
17286#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)
17287#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk
17288#define UCPD_ICR_HRSTSENTCF_Pos (5U)
17289#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)
17290#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk
17291#define UCPD_ICR_TXUNDCF_Pos (6U)
17292#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos)
17293#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk
17294#define UCPD_ICR_RXORDDETCF_Pos (9U)
17295#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos)
17296#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk
17297#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
17298#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)
17299#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk
17300#define UCPD_ICR_RXOVRCF_Pos (11U)
17301#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos)
17302#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk
17303#define UCPD_ICR_RXMSGENDCF_Pos (12U)
17304#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)
17305#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk
17306#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
17307#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)
17308#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk
17309#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
17310#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)
17311#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk
17312#define UCPD_ICR_FRSEVTCF_Pos (20U)
17313#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos)
17314#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk
17316/******************** Bits definition for UCPD_TXORDSET register **************/
17317#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
17318#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)
17319#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk
17321/******************** Bits definition for UCPD_TXPAYSZ register ****************/
17322#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
17323#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)
17324#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk
17326/******************** Bits definition for UCPD_TXDR register *******************/
17327#define UCPD_TXDR_TXDATA_Pos (0U)
17328#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos)
17329#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk
17331/******************** Bits definition for UCPD_RXORDSET register **************/
17332#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
17333#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos)
17334#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk
17335#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos)
17336#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos)
17337#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos)
17338#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
17339#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)
17340#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk
17341#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
17342#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)
17343#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk
17345/******************** Bits definition for UCPD_RXPAYSZ register ****************/
17346#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
17347#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)
17348#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk
17350/******************** Bits definition for UCPD_RXDR register *******************/
17351#define UCPD_RXDR_RXDATA_Pos (0U)
17352#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos)
17353#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk
17355/******************** Bits definition for UCPD_RXORDEXT1 register **************/
17356#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
17357#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)
17358#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk
17360/******************** Bits definition for UCPD_RXORDEXT2 register **************/
17361#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
17362#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)
17363#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk
17365/******************************************************************************/
17366/* */
17367/* Window WATCHDOG */
17368/* */
17369/******************************************************************************/
17370/******************* Bit definition for WWDG_CR register ********************/
17371#define WWDG_CR_T_Pos (0U)
17372#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
17373#define WWDG_CR_T WWDG_CR_T_Msk
17374#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
17375#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
17376#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
17377#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
17378#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
17379#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
17380#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
17382#define WWDG_CR_WDGA_Pos (7U)
17383#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
17384#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
17386/******************* Bit definition for WWDG_CFR register *******************/
17387#define WWDG_CFR_W_Pos (0U)
17388#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
17389#define WWDG_CFR_W WWDG_CFR_W_Msk
17390#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
17391#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
17392#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
17393#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
17394#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
17395#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
17396#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
17398#define WWDG_CFR_WDGTB_Pos (11U)
17399#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)
17400#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
17401#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
17402#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
17403#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)
17405#define WWDG_CFR_EWI_Pos (9U)
17406#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
17407#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
17409/******************* Bit definition for WWDG_SR register ********************/
17410#define WWDG_SR_EWIF_Pos (0U)
17411#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
17412#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
17426/******************************* ADC Instances ********************************/
17427#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17428 ((INSTANCE) == ADC2) || \
17429 ((INSTANCE) == ADC3) || \
17430 ((INSTANCE) == ADC4) || \
17431 ((INSTANCE) == ADC5))
17432
17433#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17434 ((INSTANCE) == ADC3))
17435
17436#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
17437 ((INSTANCE) == ADC345_COMMON) )
17438
17439
17440/******************************** FDCAN Instances ******************************/
17441#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
17442 ((INSTANCE) == FDCAN2) || \
17443 ((INSTANCE) == FDCAN3))
17444
17445#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
17446/******************************** COMP Instances ******************************/
17447#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
17448 ((INSTANCE) == COMP2) || \
17449 ((INSTANCE) == COMP3) || \
17450 ((INSTANCE) == COMP4) || \
17451 ((INSTANCE) == COMP5) || \
17452 ((INSTANCE) == COMP6) || \
17453 ((INSTANCE) == COMP7))
17454
17455/******************************* CORDIC Instances *****************************/
17456#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
17457
17458/******************************* CRC Instances ********************************/
17459#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
17460
17461/******************************* DAC Instances ********************************/
17462#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
17463 ((INSTANCE) == DAC2) || \
17464 ((INSTANCE) == DAC3) || \
17465 ((INSTANCE) == DAC4))
17466
17467
17468/******************************** DMA Instances *******************************/
17469#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
17470 ((INSTANCE) == DMA1_Channel2) || \
17471 ((INSTANCE) == DMA1_Channel3) || \
17472 ((INSTANCE) == DMA1_Channel4) || \
17473 ((INSTANCE) == DMA1_Channel5) || \
17474 ((INSTANCE) == DMA1_Channel6) || \
17475 ((INSTANCE) == DMA1_Channel7) || \
17476 ((INSTANCE) == DMA1_Channel8) || \
17477 ((INSTANCE) == DMA2_Channel1) || \
17478 ((INSTANCE) == DMA2_Channel2) || \
17479 ((INSTANCE) == DMA2_Channel3) || \
17480 ((INSTANCE) == DMA2_Channel4) || \
17481 ((INSTANCE) == DMA2_Channel5) || \
17482 ((INSTANCE) == DMA2_Channel6) || \
17483 ((INSTANCE) == DMA2_Channel7) || \
17484 ((INSTANCE) == DMA2_Channel8))
17485
17486#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
17487 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
17488 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
17489 ((INSTANCE) == DMAMUX1_RequestGenerator3))
17490
17491/******************************* FMAC Instances *******************************/
17492#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
17493
17494/******************************* GPIO Instances *******************************/
17495#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
17496 ((INSTANCE) == GPIOB) || \
17497 ((INSTANCE) == GPIOC) || \
17498 ((INSTANCE) == GPIOD) || \
17499 ((INSTANCE) == GPIOE) || \
17500 ((INSTANCE) == GPIOF) || \
17501 ((INSTANCE) == GPIOG))
17502
17503/******************************* GPIO AF Instances ****************************/
17504#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17505
17506/**************************** GPIO Lock Instances *****************************/
17507#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17508
17509/******************************** I2C Instances *******************************/
17510#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17511 ((INSTANCE) == I2C2) || \
17512 ((INSTANCE) == I2C3) || \
17513 ((INSTANCE) == I2C4))
17514
17515/****************** I2C Instances : wakeup capability from stop modes *********/
17516#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
17517
17518/****************************** OPAMP Instances *******************************/
17519#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
17520 ((INSTANCE) == OPAMP2) || \
17521 ((INSTANCE) == OPAMP3) || \
17522 ((INSTANCE) == OPAMP4) || \
17523 ((INSTANCE) == OPAMP5) || \
17524 ((INSTANCE) == OPAMP6))
17525
17526/******************************** PCD Instances *******************************/
17527#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
17528
17529/******************************* QSPI Instances *******************************/
17530#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
17531
17532/******************************* RNG Instances ********************************/
17533#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
17534
17535/****************************** RTC Instances *********************************/
17536#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
17537
17538#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
17539
17540/****************************** SMBUS Instances *******************************/
17541#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17542 ((INSTANCE) == I2C2) || \
17543 ((INSTANCE) == I2C3) || \
17544 ((INSTANCE) == I2C4))
17545
17546/******************************** SAI Instances *******************************/
17547#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
17548
17549/******************************** SPI Instances *******************************/
17550#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
17551 ((INSTANCE) == SPI2) || \
17552 ((INSTANCE) == SPI3) || \
17553 ((INSTANCE) == SPI4))
17554
17555/******************************** I2S Instances *******************************/
17556#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
17557 ((__INSTANCE__) == SPI3))
17558
17559/****************** LPTIM Instances : All supported instances *****************/
17560#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
17561
17562/****************** LPTIM Instances : supporting encoder interface **************/
17563#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
17564
17565/****************** LPTIM Instances : All supported instances *****************/
17566#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
17567
17568/****************** TIM Instances : All supported instances *******************/
17569#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17570 ((INSTANCE) == TIM2) || \
17571 ((INSTANCE) == TIM3) || \
17572 ((INSTANCE) == TIM4) || \
17573 ((INSTANCE) == TIM5) || \
17574 ((INSTANCE) == TIM6) || \
17575 ((INSTANCE) == TIM7) || \
17576 ((INSTANCE) == TIM8) || \
17577 ((INSTANCE) == TIM15) || \
17578 ((INSTANCE) == TIM16) || \
17579 ((INSTANCE) == TIM17) || \
17580 ((INSTANCE) == TIM20))
17581
17582/****************** TIM Instances : supporting 32 bits counter ****************/
17583
17584#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
17585 ((INSTANCE) == TIM5))
17586
17587/****************** TIM Instances : supporting the break function *************/
17588#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17589 ((INSTANCE) == TIM8) || \
17590 ((INSTANCE) == TIM15) || \
17591 ((INSTANCE) == TIM16) || \
17592 ((INSTANCE) == TIM17) || \
17593 ((INSTANCE) == TIM20))
17594
17595/************** TIM Instances : supporting Break source selection *************/
17596#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17597 ((INSTANCE) == TIM8) || \
17598 ((INSTANCE) == TIM15) || \
17599 ((INSTANCE) == TIM16) || \
17600 ((INSTANCE) == TIM17) || \
17601 ((INSTANCE) == TIM20))
17602
17603/****************** TIM Instances : supporting 2 break inputs *****************/
17604#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17605 ((INSTANCE) == TIM8) || \
17606 ((INSTANCE) == TIM20))
17607
17608/************* TIM Instances : at least 1 capture/compare channel *************/
17609#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17610 ((INSTANCE) == TIM2) || \
17611 ((INSTANCE) == TIM3) || \
17612 ((INSTANCE) == TIM4) || \
17613 ((INSTANCE) == TIM5) || \
17614 ((INSTANCE) == TIM8) || \
17615 ((INSTANCE) == TIM15) || \
17616 ((INSTANCE) == TIM16) || \
17617 ((INSTANCE) == TIM17) || \
17618 ((INSTANCE) == TIM20))
17619
17620/************ TIM Instances : at least 2 capture/compare channels *************/
17621#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17622 ((INSTANCE) == TIM2) || \
17623 ((INSTANCE) == TIM3) || \
17624 ((INSTANCE) == TIM4) || \
17625 ((INSTANCE) == TIM5) || \
17626 ((INSTANCE) == TIM8) || \
17627 ((INSTANCE) == TIM15) || \
17628 ((INSTANCE) == TIM20))
17629
17630/************ TIM Instances : at least 3 capture/compare channels *************/
17631#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17632 ((INSTANCE) == TIM2) || \
17633 ((INSTANCE) == TIM3) || \
17634 ((INSTANCE) == TIM4) || \
17635 ((INSTANCE) == TIM5) || \
17636 ((INSTANCE) == TIM8) || \
17637 ((INSTANCE) == TIM20))
17638
17639/************ TIM Instances : at least 4 capture/compare channels *************/
17640#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17641 ((INSTANCE) == TIM2) || \
17642 ((INSTANCE) == TIM3) || \
17643 ((INSTANCE) == TIM4) || \
17644 ((INSTANCE) == TIM5) || \
17645 ((INSTANCE) == TIM8) || \
17646 ((INSTANCE) == TIM20))
17647
17648/****************** TIM Instances : at least 5 capture/compare channels *******/
17649#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17650 ((INSTANCE) == TIM8) || \
17651 ((INSTANCE) == TIM20))
17652
17653/****************** TIM Instances : at least 6 capture/compare channels *******/
17654#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17655 ((INSTANCE) == TIM8) || \
17656 ((INSTANCE) == TIM20))
17657
17658/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
17659#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17660 ((INSTANCE) == TIM8) || \
17661 ((INSTANCE) == TIM15) || \
17662 ((INSTANCE) == TIM16) || \
17663 ((INSTANCE) == TIM17) || \
17664 ((INSTANCE) == TIM20))
17665
17666/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
17667#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17668 ((INSTANCE) == TIM2) || \
17669 ((INSTANCE) == TIM3) || \
17670 ((INSTANCE) == TIM4) || \
17671 ((INSTANCE) == TIM5) || \
17672 ((INSTANCE) == TIM6) || \
17673 ((INSTANCE) == TIM7) || \
17674 ((INSTANCE) == TIM8) || \
17675 ((INSTANCE) == TIM15) || \
17676 ((INSTANCE) == TIM16) || \
17677 ((INSTANCE) == TIM17) || \
17678 ((INSTANCE) == TIM20))
17679
17680/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
17681#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17682 ((INSTANCE) == TIM2) || \
17683 ((INSTANCE) == TIM3) || \
17684 ((INSTANCE) == TIM4) || \
17685 ((INSTANCE) == TIM5) || \
17686 ((INSTANCE) == TIM8) || \
17687 ((INSTANCE) == TIM15) || \
17688 ((INSTANCE) == TIM16) || \
17689 ((INSTANCE) == TIM17) || \
17690 ((INSTANCE) == TIM20))
17691
17692/******************** TIM Instances : DMA burst feature ***********************/
17693#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17694 ((INSTANCE) == TIM2) || \
17695 ((INSTANCE) == TIM3) || \
17696 ((INSTANCE) == TIM4) || \
17697 ((INSTANCE) == TIM5) || \
17698 ((INSTANCE) == TIM8) || \
17699 ((INSTANCE) == TIM15) || \
17700 ((INSTANCE) == TIM16) || \
17701 ((INSTANCE) == TIM17) || \
17702 ((INSTANCE) == TIM20))
17703
17704/******************* TIM Instances : output(s) available **********************/
17705#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
17706 ((((INSTANCE) == TIM1) && \
17707 (((CHANNEL) == TIM_CHANNEL_1) || \
17708 ((CHANNEL) == TIM_CHANNEL_2) || \
17709 ((CHANNEL) == TIM_CHANNEL_3) || \
17710 ((CHANNEL) == TIM_CHANNEL_4) || \
17711 ((CHANNEL) == TIM_CHANNEL_5) || \
17712 ((CHANNEL) == TIM_CHANNEL_6))) \
17713 || \
17714 (((INSTANCE) == TIM2) && \
17715 (((CHANNEL) == TIM_CHANNEL_1) || \
17716 ((CHANNEL) == TIM_CHANNEL_2) || \
17717 ((CHANNEL) == TIM_CHANNEL_3) || \
17718 ((CHANNEL) == TIM_CHANNEL_4))) \
17719 || \
17720 (((INSTANCE) == TIM3) && \
17721 (((CHANNEL) == TIM_CHANNEL_1) || \
17722 ((CHANNEL) == TIM_CHANNEL_2) || \
17723 ((CHANNEL) == TIM_CHANNEL_3) || \
17724 ((CHANNEL) == TIM_CHANNEL_4))) \
17725 || \
17726 (((INSTANCE) == TIM4) && \
17727 (((CHANNEL) == TIM_CHANNEL_1) || \
17728 ((CHANNEL) == TIM_CHANNEL_2) || \
17729 ((CHANNEL) == TIM_CHANNEL_3) || \
17730 ((CHANNEL) == TIM_CHANNEL_4))) \
17731 || \
17732 (((INSTANCE) == TIM5) && \
17733 (((CHANNEL) == TIM_CHANNEL_1) || \
17734 ((CHANNEL) == TIM_CHANNEL_2) || \
17735 ((CHANNEL) == TIM_CHANNEL_3) || \
17736 ((CHANNEL) == TIM_CHANNEL_4))) \
17737 || \
17738 (((INSTANCE) == TIM8) && \
17739 (((CHANNEL) == TIM_CHANNEL_1) || \
17740 ((CHANNEL) == TIM_CHANNEL_2) || \
17741 ((CHANNEL) == TIM_CHANNEL_3) || \
17742 ((CHANNEL) == TIM_CHANNEL_4) || \
17743 ((CHANNEL) == TIM_CHANNEL_5) || \
17744 ((CHANNEL) == TIM_CHANNEL_6))) \
17745 || \
17746 (((INSTANCE) == TIM15) && \
17747 (((CHANNEL) == TIM_CHANNEL_1) || \
17748 ((CHANNEL) == TIM_CHANNEL_2))) \
17749 || \
17750 (((INSTANCE) == TIM16) && \
17751 (((CHANNEL) == TIM_CHANNEL_1))) \
17752 || \
17753 (((INSTANCE) == TIM17) && \
17754 (((CHANNEL) == TIM_CHANNEL_1))) \
17755 || \
17756 (((INSTANCE) == TIM20) && \
17757 (((CHANNEL) == TIM_CHANNEL_1) || \
17758 ((CHANNEL) == TIM_CHANNEL_2) || \
17759 ((CHANNEL) == TIM_CHANNEL_3) || \
17760 ((CHANNEL) == TIM_CHANNEL_4) || \
17761 ((CHANNEL) == TIM_CHANNEL_5) || \
17762 ((CHANNEL) == TIM_CHANNEL_6))))
17763
17764/****************** TIM Instances : supporting complementary output(s) ********/
17765#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
17766 ((((INSTANCE) == TIM1) && \
17767 (((CHANNEL) == TIM_CHANNEL_1) || \
17768 ((CHANNEL) == TIM_CHANNEL_2) || \
17769 ((CHANNEL) == TIM_CHANNEL_3) || \
17770 ((CHANNEL) == TIM_CHANNEL_4))) \
17771 || \
17772 (((INSTANCE) == TIM8) && \
17773 (((CHANNEL) == TIM_CHANNEL_1) || \
17774 ((CHANNEL) == TIM_CHANNEL_2) || \
17775 ((CHANNEL) == TIM_CHANNEL_3) || \
17776 ((CHANNEL) == TIM_CHANNEL_4))) \
17777 || \
17778 (((INSTANCE) == TIM15) && \
17779 ((CHANNEL) == TIM_CHANNEL_1)) \
17780 || \
17781 (((INSTANCE) == TIM16) && \
17782 ((CHANNEL) == TIM_CHANNEL_1)) \
17783 || \
17784 (((INSTANCE) == TIM17) && \
17785 ((CHANNEL) == TIM_CHANNEL_1)) \
17786 || \
17787 (((INSTANCE) == TIM20) && \
17788 (((CHANNEL) == TIM_CHANNEL_1) || \
17789 ((CHANNEL) == TIM_CHANNEL_2) || \
17790 ((CHANNEL) == TIM_CHANNEL_3) || \
17791 ((CHANNEL) == TIM_CHANNEL_4))))
17792
17793/****************** TIM Instances : supporting clock division *****************/
17794#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17795 ((INSTANCE) == TIM2) || \
17796 ((INSTANCE) == TIM3) || \
17797 ((INSTANCE) == TIM4) || \
17798 ((INSTANCE) == TIM5) || \
17799 ((INSTANCE) == TIM8) || \
17800 ((INSTANCE) == TIM15) || \
17801 ((INSTANCE) == TIM16) || \
17802 ((INSTANCE) == TIM17) || \
17803 ((INSTANCE) == TIM20))
17804
17805/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
17806#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17807 ((INSTANCE) == TIM2) || \
17808 ((INSTANCE) == TIM3) || \
17809 ((INSTANCE) == TIM4) || \
17810 ((INSTANCE) == TIM5) || \
17811 ((INSTANCE) == TIM8) || \
17812 ((INSTANCE) == TIM20))
17813
17814/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
17815#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17816 ((INSTANCE) == TIM2) || \
17817 ((INSTANCE) == TIM3) || \
17818 ((INSTANCE) == TIM4) || \
17819 ((INSTANCE) == TIM5) || \
17820 ((INSTANCE) == TIM8) || \
17821 ((INSTANCE) == TIM20))
17822
17823/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
17824#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17825 ((INSTANCE) == TIM2) || \
17826 ((INSTANCE) == TIM3) || \
17827 ((INSTANCE) == TIM4) || \
17828 ((INSTANCE) == TIM5) || \
17829 ((INSTANCE) == TIM8) || \
17830 ((INSTANCE) == TIM15)|| \
17831 ((INSTANCE) == TIM20))
17832
17833/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
17834#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17835 ((INSTANCE) == TIM2) || \
17836 ((INSTANCE) == TIM3) || \
17837 ((INSTANCE) == TIM4) || \
17838 ((INSTANCE) == TIM5) || \
17839 ((INSTANCE) == TIM8) || \
17840 ((INSTANCE) == TIM15)|| \
17841 ((INSTANCE) == TIM20))
17842
17843/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
17844#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17845 ((INSTANCE) == TIM8) || \
17846 ((INSTANCE) == TIM20))
17847
17848/****************** TIM Instances : supporting commutation event generation ***/
17849#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17850 ((INSTANCE) == TIM8) || \
17851 ((INSTANCE) == TIM15) || \
17852 ((INSTANCE) == TIM16) || \
17853 ((INSTANCE) == TIM17) || \
17854 ((INSTANCE) == TIM20))
17855
17856/****************** TIM Instances : supporting counting mode selection ********/
17857#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17858 ((INSTANCE) == TIM2) || \
17859 ((INSTANCE) == TIM3) || \
17860 ((INSTANCE) == TIM4) || \
17861 ((INSTANCE) == TIM5) || \
17862 ((INSTANCE) == TIM8) || \
17863 ((INSTANCE) == TIM20))
17864
17865/****************** TIM Instances : supporting encoder interface **************/
17866#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17867 ((INSTANCE) == TIM2) || \
17868 ((INSTANCE) == TIM3) || \
17869 ((INSTANCE) == TIM4) || \
17870 ((INSTANCE) == TIM5) || \
17871 ((INSTANCE) == TIM8) || \
17872 ((INSTANCE) == TIM20))
17873
17874/****************** TIM Instances : supporting Hall sensor interface **********/
17875#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17876 ((INSTANCE) == TIM2) || \
17877 ((INSTANCE) == TIM3) || \
17878 ((INSTANCE) == TIM4) || \
17879 ((INSTANCE) == TIM5) || \
17880 ((INSTANCE) == TIM8) || \
17881 ((INSTANCE) == TIM15) || \
17882 ((INSTANCE) == TIM20))
17883
17884/**************** TIM Instances : external trigger input available ************/
17885#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17886 ((INSTANCE) == TIM2) || \
17887 ((INSTANCE) == TIM3) || \
17888 ((INSTANCE) == TIM4) || \
17889 ((INSTANCE) == TIM5) || \
17890 ((INSTANCE) == TIM8) || \
17891 ((INSTANCE) == TIM20))
17892
17893/************* TIM Instances : supporting ETR source selection ***************/
17894#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17895 ((INSTANCE) == TIM2) || \
17896 ((INSTANCE) == TIM3) || \
17897 ((INSTANCE) == TIM4) || \
17898 ((INSTANCE) == TIM5) || \
17899 ((INSTANCE) == TIM8) || \
17900 ((INSTANCE) == TIM20))
17901
17902/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
17903#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17904 ((INSTANCE) == TIM2) || \
17905 ((INSTANCE) == TIM3) || \
17906 ((INSTANCE) == TIM4) || \
17907 ((INSTANCE) == TIM5) || \
17908 ((INSTANCE) == TIM6) || \
17909 ((INSTANCE) == TIM7) || \
17910 ((INSTANCE) == TIM8) || \
17911 ((INSTANCE) == TIM15) || \
17912 ((INSTANCE) == TIM20))
17913
17914/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
17915#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17916 ((INSTANCE) == TIM2) || \
17917 ((INSTANCE) == TIM3) || \
17918 ((INSTANCE) == TIM4) || \
17919 ((INSTANCE) == TIM5) || \
17920 ((INSTANCE) == TIM8) || \
17921 ((INSTANCE) == TIM15) || \
17922 ((INSTANCE) == TIM20))
17923
17924/****************** TIM Instances : supporting OCxREF clear *******************/
17925#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17926 ((INSTANCE) == TIM2) || \
17927 ((INSTANCE) == TIM3) || \
17928 ((INSTANCE) == TIM4) || \
17929 ((INSTANCE) == TIM5) || \
17930 ((INSTANCE) == TIM8) || \
17931 ((INSTANCE) == TIM15) || \
17932 ((INSTANCE) == TIM16) || \
17933 ((INSTANCE) == TIM17) || \
17934 ((INSTANCE) == TIM20))
17935
17936/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
17937#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17938 ((INSTANCE) == TIM2) || \
17939 ((INSTANCE) == TIM3) || \
17940 ((INSTANCE) == TIM8) || \
17941 ((INSTANCE) == TIM15) || \
17942 ((INSTANCE) == TIM16) || \
17943 ((INSTANCE) == TIM17) || \
17944 ((INSTANCE) == TIM20))
17945
17946/****************** TIM Instances : remapping capability **********************/
17947#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17948 ((INSTANCE) == TIM2) || \
17949 ((INSTANCE) == TIM3) || \
17950 ((INSTANCE) == TIM4) || \
17951 ((INSTANCE) == TIM5) || \
17952 ((INSTANCE) == TIM8) || \
17953 ((INSTANCE) == TIM20))
17954
17955/****************** TIM Instances : supporting repetition counter *************/
17956#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17957 ((INSTANCE) == TIM8) || \
17958 ((INSTANCE) == TIM15) || \
17959 ((INSTANCE) == TIM16) || \
17960 ((INSTANCE) == TIM17) || \
17961 ((INSTANCE) == TIM20))
17962
17963/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
17964#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17965 ((INSTANCE) == TIM8) || \
17966 ((INSTANCE) == TIM20))
17967
17968/******************* TIM Instances : Timer input XOR function *****************/
17969#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17970 ((INSTANCE) == TIM2) || \
17971 ((INSTANCE) == TIM3) || \
17972 ((INSTANCE) == TIM4) || \
17973 ((INSTANCE) == TIM5) || \
17974 ((INSTANCE) == TIM8) || \
17975 ((INSTANCE) == TIM15) || \
17976 ((INSTANCE) == TIM20))
17977
17978/******************* TIM Instances : Timer input selection ********************/
17979#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17980 ((INSTANCE) == TIM2) || \
17981 ((INSTANCE) == TIM3) || \
17982 ((INSTANCE) == TIM4) || \
17983 ((INSTANCE) == TIM5) || \
17984 ((INSTANCE) == TIM8) || \
17985 ((INSTANCE) == TIM15) || \
17986 ((INSTANCE) == TIM16) || \
17987 ((INSTANCE) == TIM17) || \
17988 ((INSTANCE) == TIM20))
17989
17990/****************** TIM Instances : Advanced timer instances *******************/
17991#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17992 ((INSTANCE) == TIM8) || \
17993 ((INSTANCE) == TIM20))
17994
17995/****************** TIM Instances : supporting HSE/32 request instances *******************/
17996#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
17997 ((INSTANCE) == TIM17))
17998
17999/****************************** HRTIM Instances *******************************/
18000#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
18001
18002/******************** USART Instances : Synchronous mode **********************/
18003#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18004 ((INSTANCE) == USART2) || \
18005 ((INSTANCE) == USART3))
18006
18007/******************** UART Instances : Asynchronous mode **********************/
18008#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18009 ((INSTANCE) == USART2) || \
18010 ((INSTANCE) == USART3) || \
18011 ((INSTANCE) == UART4) || \
18012 ((INSTANCE) == UART5))
18013
18014/*********************** UART Instances : FIFO mode ***************************/
18015#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18016 ((INSTANCE) == USART2) || \
18017 ((INSTANCE) == USART3) || \
18018 ((INSTANCE) == UART4) || \
18019 ((INSTANCE) == UART5) || \
18020 ((INSTANCE) == LPUART1))
18021
18022/*********************** UART Instances : SPI Slave mode **********************/
18023#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18024 ((INSTANCE) == USART2) || \
18025 ((INSTANCE) == USART3))
18026
18027/****************** UART Instances : Auto Baud Rate detection ****************/
18028#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18029 ((INSTANCE) == USART2) || \
18030 ((INSTANCE) == USART3) || \
18031 ((INSTANCE) == UART4) || \
18032 ((INSTANCE) == UART5))
18033
18034/****************** UART Instances : Driver Enable *****************/
18035#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18036 ((INSTANCE) == USART2) || \
18037 ((INSTANCE) == USART3) || \
18038 ((INSTANCE) == UART4) || \
18039 ((INSTANCE) == UART5) || \
18040 ((INSTANCE) == LPUART1))
18041
18042/******************** UART Instances : Half-Duplex mode **********************/
18043#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18044 ((INSTANCE) == USART2) || \
18045 ((INSTANCE) == USART3) || \
18046 ((INSTANCE) == UART4) || \
18047 ((INSTANCE) == UART5) || \
18048 ((INSTANCE) == LPUART1))
18049
18050/****************** UART Instances : Hardware Flow control ********************/
18051#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18052 ((INSTANCE) == USART2) || \
18053 ((INSTANCE) == USART3) || \
18054 ((INSTANCE) == UART4) || \
18055 ((INSTANCE) == UART5) || \
18056 ((INSTANCE) == LPUART1))
18057
18058/******************** UART Instances : LIN mode **********************/
18059#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18060 ((INSTANCE) == USART2) || \
18061 ((INSTANCE) == USART3) || \
18062 ((INSTANCE) == UART4) || \
18063 ((INSTANCE) == UART5))
18064
18065/******************** UART Instances : Wake-up from Stop mode **********************/
18066#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18067 ((INSTANCE) == USART2) || \
18068 ((INSTANCE) == USART3) || \
18069 ((INSTANCE) == UART4) || \
18070 ((INSTANCE) == UART5) || \
18071 ((INSTANCE) == LPUART1))
18072
18073/*********************** UART Instances : IRDA mode ***************************/
18074#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18075 ((INSTANCE) == USART2) || \
18076 ((INSTANCE) == USART3) || \
18077 ((INSTANCE) == UART4) || \
18078 ((INSTANCE) == UART5))
18079
18080/********************* USART Instances : Smard card mode ***********************/
18081#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18082 ((INSTANCE) == USART2) || \
18083 ((INSTANCE) == USART3))
18084
18085/******************** LPUART Instance *****************************************/
18086#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
18087
18088/****************************** IWDG Instances ********************************/
18089#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
18090
18091/****************************** WWDG Instances ********************************/
18092#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
18093
18094/****************************** UCPD Instances ********************************/
18095#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
18096
18097/******************************* USB Instances *******************************/
18098#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
18099
18105/******************************************************************************/
18106/* For a painless codes migration between the STM32G4xx device product */
18107/* lines, the aliases defined below are put in place to overcome the */
18108/* differences in the interrupt handlers and IRQn definitions. */
18109/* No need to update developed interrupt code when moving across */
18110/* product lines within the same STM32G4 Family */
18111/******************************************************************************/
18112
18113/* Aliases for __IRQn */
18114
18115/* Aliases for __IRQHandler */
18116
18117#ifdef __cplusplus
18118}
18119#endif /* __cplusplus */
18120
18121#endif /* __STM32G474xx_H */
18122
__IO
#define __IO
Definition: core_armv81mml.h:277
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32G4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32g474xx.h:66
CRS_IRQn
@ CRS_IRQn
Definition: stm32g474xx.h:153
TIM8_TRG_COM_IRQn
@ TIM8_TRG_COM_IRQn
Definition: stm32g474xx.h:123
FMAC_IRQn
@ FMAC_IRQn
Definition: stm32g474xx.h:178
DMA2_Channel8_IRQn
@ DMA2_Channel8_IRQn
Definition: stm32g474xx.h:176
COMP1_2_3_IRQn
@ COMP1_2_3_IRQn
Definition: stm32g474xx.h:142
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32g474xx.h:75
FDCAN3_IT1_IRQn
@ FDCAN3_IT1_IRQn
Definition: stm32g474xx.h:166
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32g474xx.h:86
DMA2_Channel4_IRQn
@ DMA2_Channel4_IRQn
Definition: stm32g474xx.h:137
HRTIM1_TIMB_IRQn
@ HRTIM1_TIMB_IRQn
Definition: stm32g474xx.h:147
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32g474xx.h:81
ADC1_2_IRQn
@ ADC1_2_IRQn
Definition: stm32g474xx.h:96
RTC_TAMP_LSECSS_IRQn
@ RTC_TAMP_LSECSS_IRQn
Definition: stm32g474xx.h:80
HRTIM1_Master_IRQn
@ HRTIM1_Master_IRQn
Definition: stm32g474xx.h:145
DMA1_Channel2_IRQn
@ DMA1_Channel2_IRQn
Definition: stm32g474xx.h:90
HRTIM1_TIMF_IRQn
@ HRTIM1_TIMF_IRQn
Definition: stm32g474xx.h:152
ADC4_IRQn
@ ADC4_IRQn
Definition: stm32g474xx.h:139
UCPD1_IRQn
@ UCPD1_IRQn
Definition: stm32g474xx.h:141
USBWakeUp_IRQn
@ USBWakeUp_IRQn
Definition: stm32g474xx.h:120
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32g474xx.h:110
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32g474xx.h:111
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32g474xx.h:70
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32g474xx.h:154
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32g474xx.h:108
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32g474xx.h:106
DMA1_Channel1_IRQn
@ DMA1_Channel1_IRQn
Definition: stm32g474xx.h:89
DMA1_Channel3_IRQn
@ DMA1_Channel3_IRQn
Definition: stm32g474xx.h:91
DMA1_Channel8_IRQn
@ DMA1_Channel8_IRQn
Definition: stm32g474xx.h:173
FDCAN1_IT0_IRQn
@ FDCAN1_IT0_IRQn
Definition: stm32g474xx.h:99
USART2_IRQn
@ USART2_IRQn
Definition: stm32g474xx.h:116
USB_LP_IRQn
@ USB_LP_IRQn
Definition: stm32g474xx.h:98
DMA2_Channel7_IRQn
@ DMA2_Channel7_IRQn
Definition: stm32g474xx.h:175
HRTIM1_FLT_IRQn
@ HRTIM1_FLT_IRQn
Definition: stm32g474xx.h:151
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32g474xx.h:73
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32g474xx.h:129
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32g474xx.h:114
FDCAN2_IT0_IRQn
@ FDCAN2_IT0_IRQn
Definition: stm32g474xx.h:163
RCC_IRQn
@ RCC_IRQn
Definition: stm32g474xx.h:83
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32g474xx.h:125
TIM1_TRG_COM_TIM17_IRQn
@ TIM1_TRG_COM_TIM17_IRQn
Definition: stm32g474xx.h:104
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32g474xx.h:132
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32g474xx.h:112
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition: stm32g474xx.h:172
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32g474xx.h:124
DMA1_Channel7_IRQn
@ DMA1_Channel7_IRQn
Definition: stm32g474xx.h:95
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32g474xx.h:72
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition: stm32g474xx.h:161
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32g474xx.h:76
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32g474xx.h:170
TIM20_BRK_IRQn
@ TIM20_BRK_IRQn
Definition: stm32g474xx.h:155
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32g474xx.h:169
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32g474xx.h:71
DMA2_Channel6_IRQn
@ DMA2_Channel6_IRQn
Definition: stm32g474xx.h:174
ADC5_IRQn
@ ADC5_IRQn
Definition: stm32g474xx.h:140
TIM1_BRK_TIM15_IRQn
@ TIM1_BRK_TIM15_IRQn
Definition: stm32g474xx.h:102
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32g474xx.h:74
RNG_IRQn
@ RNG_IRQn
Definition: stm32g474xx.h:167
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32g474xx.h:82
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32g474xx.h:78
HRTIM1_TIMA_IRQn
@ HRTIM1_TIMA_IRQn
Definition: stm32g474xx.h:146
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32g474xx.h:109
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32g474xx.h:107
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32g474xx.h:118
USB_HP_IRQn
@ USB_HP_IRQn
Definition: stm32g474xx.h:97
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32g474xx.h:162
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32g474xx.h:101
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32g474xx.h:127
FPU_IRQn
@ FPU_IRQn
Definition: stm32g474xx.h:159
TIM20_CC_IRQn
@ TIM20_CC_IRQn
Definition: stm32g474xx.h:158
DMA1_Channel6_IRQn
@ DMA1_Channel6_IRQn
Definition: stm32g474xx.h:94
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32g474xx.h:113
DMAMUX_OVR_IRQn
@ DMAMUX_OVR_IRQn
Definition: stm32g474xx.h:171
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32g474xx.h:69
FMC_IRQn
@ FMC_IRQn
Definition: stm32g474xx.h:126
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32g474xx.h:84
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32g474xx.h:88
HRTIM1_TIMD_IRQn
@ HRTIM1_TIMD_IRQn
Definition: stm32g474xx.h:149
HRTIM1_TIMC_IRQn
@ HRTIM1_TIMC_IRQn
Definition: stm32g474xx.h:148
DMA2_Channel1_IRQn
@ DMA2_Channel1_IRQn
Definition: stm32g474xx.h:134
DMA1_Channel5_IRQn
@ DMA1_Channel5_IRQn
Definition: stm32g474xx.h:93
TIM8_BRK_IRQn
@ TIM8_BRK_IRQn
Definition: stm32g474xx.h:121
DMA2_Channel5_IRQn
@ DMA2_Channel5_IRQn
Definition: stm32g474xx.h:138
UART5_IRQn
@ UART5_IRQn
Definition: stm32g474xx.h:131
DMA2_Channel2_IRQn
@ DMA2_Channel2_IRQn
Definition: stm32g474xx.h:135
COMP7_IRQn
@ COMP7_IRQn
Definition: stm32g474xx.h:144
TIM1_UP_TIM16_IRQn
@ TIM1_UP_TIM16_IRQn
Definition: stm32g474xx.h:103
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition: stm32g474xx.h:160
USART1_IRQn
@ USART1_IRQn
Definition: stm32g474xx.h:115
DMA2_Channel3_IRQn
@ DMA2_Channel3_IRQn
Definition: stm32g474xx.h:136
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32g474xx.h:87
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32g474xx.h:68
TIM7_DAC_IRQn
@ TIM7_DAC_IRQn
Definition: stm32g474xx.h:133
UART4_IRQn
@ UART4_IRQn
Definition: stm32g474xx.h:130
PVD_PVM_IRQn
@ PVD_PVM_IRQn
Definition: stm32g474xx.h:79
TIM20_TRG_COM_IRQn
@ TIM20_TRG_COM_IRQn
Definition: stm32g474xx.h:157
DMA1_Channel4_IRQn
@ DMA1_Channel4_IRQn
Definition: stm32g474xx.h:92
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32g474xx.h:85
FDCAN3_IT0_IRQn
@ FDCAN3_IT0_IRQn
Definition: stm32g474xx.h:165
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32g474xx.h:128
TIM20_UP_IRQn
@ TIM20_UP_IRQn
Definition: stm32g474xx.h:156
HRTIM1_TIME_IRQn
@ HRTIM1_TIME_IRQn
Definition: stm32g474xx.h:150
TIM8_UP_IRQn
@ TIM8_UP_IRQn
Definition: stm32g474xx.h:122
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32g474xx.h:105
COMP4_5_6_IRQn
@ COMP4_5_6_IRQn
Definition: stm32g474xx.h:143
FDCAN1_IT1_IRQn
@ FDCAN1_IT1_IRQn
Definition: stm32g474xx.h:100
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32g474xx.h:168
CORDIC_IRQn
@ CORDIC_IRQn
Definition: stm32g474xx.h:177
USART3_IRQn
@ USART3_IRQn
Definition: stm32g474xx.h:117
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32g474xx.h:119
FDCAN2_IT1_IRQn
@ FDCAN2_IT1_IRQn
Definition: stm32g474xx.h:164
ADC_Common_TypeDef
Definition: stm32g474xx.h:241
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32g474xx.h:244
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32g474xx.h:245
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32g474xx.h:242
ADC_Common_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32g474xx.h:243
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32g474xx.h:198
ADC_TypeDef::GCOMP
__IO uint32_t GCOMP
Definition: stm32g474xx.h:237
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32g474xx.h:225
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32g474xx.h:202
ADC_TypeDef::TR2
__IO uint32_t TR2
Definition: stm32g474xx.h:208
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32g474xx.h:211
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32g474xx.h:227
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32g474xx.h:215
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition: stm32g474xx.h:220
ADC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32g474xx.h:210
ADC_TypeDef::IER
__IO uint32_t IER
Definition: stm32g474xx.h:200
ADC_TypeDef::OFR3
__IO uint32_t OFR3
Definition: stm32g474xx.h:222
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32g474xx.h:205
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32g474xx.h:218
ADC_TypeDef::OFR2
__IO uint32_t OFR2
Definition: stm32g474xx.h:221
ADC_TypeDef::TR1
__IO uint32_t TR1
Definition: stm32g474xx.h:207
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32g474xx.h:228
ADC_TypeDef::SQR4
__IO uint32_t SQR4
Definition: stm32g474xx.h:214
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32g474xx.h:213
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32g474xx.h:212
ADC_TypeDef::AWD3CR
__IO uint32_t AWD3CR
Definition: stm32g474xx.h:231
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32g474xx.h:199
ADC_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:201
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition: stm32g474xx.h:235
ADC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32g474xx.h:217
ADC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32g474xx.h:206
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32g474xx.h:203
ADC_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32g474xx.h:233
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition: stm32g474xx.h:234
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32g474xx.h:226
ADC_TypeDef::AWD2CR
__IO uint32_t AWD2CR
Definition: stm32g474xx.h:230
ADC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32g474xx.h:216
ADC_TypeDef::TR3
__IO uint32_t TR3
Definition: stm32g474xx.h:209
ADC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32g474xx.h:232
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32g474xx.h:204
ADC_TypeDef::OFR4
__IO uint32_t OFR4
Definition: stm32g474xx.h:223
COMP_TypeDef
Comparator.
Definition: stm32g474xx.h:312
COMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32g474xx.h:313
CORDIC_TypeDef
CORDIC.
Definition: stm32g474xx.h:989
CORDIC_TypeDef::WDATA
__IO uint32_t WDATA
Definition: stm32g474xx.h:991
CORDIC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32g474xx.h:990
CORDIC_TypeDef::RDATA
__IO uint32_t RDATA
Definition: stm32g474xx.h:992
CRC_TypeDef
CRC calculation unit.
Definition: stm32g474xx.h:321
CRC_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32g474xx.h:323
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32g474xx.h:322
CRC_TypeDef::POL
__IO uint32_t POL
Definition: stm32g474xx.h:327
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:324
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition: stm32g474xx.h:326
CRC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32g474xx.h:325
CRS_TypeDef
Clock Recovery System.
Definition: stm32g474xx.h:334
CRS_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32g474xx.h:338
CRS_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32g474xx.h:336
CRS_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32g474xx.h:337
CRS_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:335
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32g474xx.h:346
DAC_TypeDef::SHRR
__IO uint32_t SHRR
Definition: stm32g474xx.h:366
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32g474xx.h:355
DAC_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32g474xx.h:362
DAC_TypeDef::STMODR
__IO uint32_t STMODR
Definition: stm32g474xx.h:370
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32g474xx.h:353
DAC_TypeDef::SHSR2
__IO uint32_t SHSR2
Definition: stm32g474xx.h:364
DAC_TypeDef::SHSR1
__IO uint32_t SHSR1
Definition: stm32g474xx.h:363
DAC_TypeDef::SHHR
__IO uint32_t SHHR
Definition: stm32g474xx.h:365
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32g474xx.h:354
DAC_TypeDef::STR2
__IO uint32_t STR2
Definition: stm32g474xx.h:369
DAC_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32g474xx.h:361
DAC_TypeDef::STR1
__IO uint32_t STR1
Definition: stm32g474xx.h:368
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32g474xx.h:352
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32g474xx.h:348
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32g474xx.h:357
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32g474xx.h:358
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:347
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32g474xx.h:359
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32g474xx.h:349
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32g474xx.h:356
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32g474xx.h:351
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32g474xx.h:350
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:360
DBGMCU_TypeDef
Debug MCU.
Definition: stm32g474xx.h:378
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32g474xx.h:379
DBGMCU_TypeDef::APB1FZR1
__IO uint32_t APB1FZR1
Definition: stm32g474xx.h:381
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32g474xx.h:383
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:380
DBGMCU_TypeDef::APB1FZR2
__IO uint32_t APB1FZR2
Definition: stm32g474xx.h:382
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32g474xx.h:391
DMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition: stm32g474xx.h:394
DMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32g474xx.h:392
DMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition: stm32g474xx.h:393
DMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition: stm32g474xx.h:395
DMA_TypeDef
Definition: stm32g474xx.h:399
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32g474xx.h:400
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32g474xx.h:401
DMAMUX_Channel_TypeDef
DMA Multiplexer.
Definition: stm32g474xx.h:409
DMAMUX_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32g474xx.h:410
DMAMUX_ChannelStatus_TypeDef
Definition: stm32g474xx.h:414
DMAMUX_ChannelStatus_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32g474xx.h:415
DMAMUX_ChannelStatus_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32g474xx.h:416
DMAMUX_RequestGen_TypeDef
Definition: stm32g474xx.h:420
DMAMUX_RequestGen_TypeDef::RGCR
__IO uint32_t RGCR
Definition: stm32g474xx.h:421
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32g474xx.h:425
DMAMUX_RequestGenStatus_TypeDef::RGCFR
__IO uint32_t RGCFR
Definition: stm32g474xx.h:427
DMAMUX_RequestGenStatus_TypeDef::RGSR
__IO uint32_t RGSR
Definition: stm32g474xx.h:426
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32g474xx.h:435
EXTI_TypeDef::RTSR2
__IO uint32_t RTSR2
Definition: stm32g474xx.h:446
EXTI_TypeDef::SWIER2
__IO uint32_t SWIER2
Definition: stm32g474xx.h:448
EXTI_TypeDef::SWIER1
__IO uint32_t SWIER1
Definition: stm32g474xx.h:440
EXTI_TypeDef::EMR2
__IO uint32_t EMR2
Definition: stm32g474xx.h:445
EXTI_TypeDef::EMR1
__IO uint32_t EMR1
Definition: stm32g474xx.h:437
EXTI_TypeDef::PR1
__IO uint32_t PR1
Definition: stm32g474xx.h:441
EXTI_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32g474xx.h:443
EXTI_TypeDef::FTSR2
__IO uint32_t FTSR2
Definition: stm32g474xx.h:447
EXTI_TypeDef::IMR2
__IO uint32_t IMR2
Definition: stm32g474xx.h:444
EXTI_TypeDef::IMR1
__IO uint32_t IMR1
Definition: stm32g474xx.h:436
EXTI_TypeDef::RTSR1
__IO uint32_t RTSR1
Definition: stm32g474xx.h:438
EXTI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32g474xx.h:442
EXTI_TypeDef::FTSR1
__IO uint32_t FTSR1
Definition: stm32g474xx.h:439
EXTI_TypeDef::PR2
__IO uint32_t PR2
Definition: stm32g474xx.h:449
FDCAN_Config_TypeDef
FD Controller Area Network Configuration.
Definition: stm32g474xx.h:303
FDCAN_Config_TypeDef::CKDIV
__IO uint32_t CKDIV
Definition: stm32g474xx.h:304
FDCAN_GlobalTypeDef
FD Controller Area Network.
Definition: stm32g474xx.h:253
FDCAN_GlobalTypeDef::TEST
__IO uint32_t TEST
Definition: stm32g474xx.h:258
FDCAN_GlobalTypeDef::TSCC
__IO uint32_t TSCC
Definition: stm32g474xx.h:262
FDCAN_GlobalTypeDef::ILS
__IO uint32_t ILS
Definition: stm32g474xx.h:273
FDCAN_GlobalTypeDef::ECR
__IO uint32_t ECR
Definition: stm32g474xx.h:267
FDCAN_GlobalTypeDef::TXBCF
__IO uint32_t TXBCF
Definition: stm32g474xx.h:291
FDCAN_GlobalTypeDef::RXF0A
__IO uint32_t RXF0A
Definition: stm32g474xx.h:281
FDCAN_GlobalTypeDef::TXBCR
__IO uint32_t TXBCR
Definition: stm32g474xx.h:289
FDCAN_GlobalTypeDef::RXGFC
__IO uint32_t RXGFC
Definition: stm32g474xx.h:276
FDCAN_GlobalTypeDef::IE
__IO uint32_t IE
Definition: stm32g474xx.h:272
FDCAN_GlobalTypeDef::DBTP
__IO uint32_t DBTP
Definition: stm32g474xx.h:257
FDCAN_GlobalTypeDef::NBTP
__IO uint32_t NBTP
Definition: stm32g474xx.h:261
FDCAN_GlobalTypeDef::TXBTO
__IO uint32_t TXBTO
Definition: stm32g474xx.h:290
FDCAN_GlobalTypeDef::IR
__IO uint32_t IR
Definition: stm32g474xx.h:271
FDCAN_GlobalTypeDef::ILE
__IO uint32_t ILE
Definition: stm32g474xx.h:274
FDCAN_GlobalTypeDef::TXBCIE
__IO uint32_t TXBCIE
Definition: stm32g474xx.h:293
FDCAN_GlobalTypeDef::XIDAM
__IO uint32_t XIDAM
Definition: stm32g474xx.h:277
FDCAN_GlobalTypeDef::TXBRP
__IO uint32_t TXBRP
Definition: stm32g474xx.h:287
FDCAN_GlobalTypeDef::HPMS
__IO uint32_t HPMS
Definition: stm32g474xx.h:278
FDCAN_GlobalTypeDef::TXFQS
__IO uint32_t TXFQS
Definition: stm32g474xx.h:286
FDCAN_GlobalTypeDef::TXEFA
__IO uint32_t TXEFA
Definition: stm32g474xx.h:295
FDCAN_GlobalTypeDef::RXF0S
__IO uint32_t RXF0S
Definition: stm32g474xx.h:280
FDCAN_GlobalTypeDef::TXBC
__IO uint32_t TXBC
Definition: stm32g474xx.h:285
FDCAN_GlobalTypeDef::PSR
__IO uint32_t PSR
Definition: stm32g474xx.h:268
FDCAN_GlobalTypeDef::CREL
__IO uint32_t CREL
Definition: stm32g474xx.h:254
FDCAN_GlobalTypeDef::RXF1A
__IO uint32_t RXF1A
Definition: stm32g474xx.h:283
FDCAN_GlobalTypeDef::TXEFS
__IO uint32_t TXEFS
Definition: stm32g474xx.h:294
FDCAN_GlobalTypeDef::TXBTIE
__IO uint32_t TXBTIE
Definition: stm32g474xx.h:292
FDCAN_GlobalTypeDef::TSCV
__IO uint32_t TSCV
Definition: stm32g474xx.h:263
FDCAN_GlobalTypeDef::ENDN
__IO uint32_t ENDN
Definition: stm32g474xx.h:255
FDCAN_GlobalTypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32g474xx.h:256
FDCAN_GlobalTypeDef::TDCR
__IO uint32_t TDCR
Definition: stm32g474xx.h:269
FDCAN_GlobalTypeDef::RWD
__IO uint32_t RWD
Definition: stm32g474xx.h:259
FDCAN_GlobalTypeDef::RESERVED5
uint32_t RESERVED5
Definition: stm32g474xx.h:279
FDCAN_GlobalTypeDef::RXF1S
__IO uint32_t RXF1S
Definition: stm32g474xx.h:282
FDCAN_GlobalTypeDef::CCCR
__IO uint32_t CCCR
Definition: stm32g474xx.h:260
FDCAN_GlobalTypeDef::TOCV
__IO uint32_t TOCV
Definition: stm32g474xx.h:265
FDCAN_GlobalTypeDef::TXBAR
__IO uint32_t TXBAR
Definition: stm32g474xx.h:288
FDCAN_GlobalTypeDef::TOCC
__IO uint32_t TOCC
Definition: stm32g474xx.h:264
FDCAN_GlobalTypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32g474xx.h:270
FLASH_TypeDef
FLASH Registers.
Definition: stm32g474xx.h:457
FLASH_TypeDef::PCROP2SR
__IO uint32_t PCROP2SR
Definition: stm32g474xx.h:472
FLASH_TypeDef::OPTR
__IO uint32_t OPTR
Definition: stm32g474xx.h:466
FLASH_TypeDef::PCROP2ER
__IO uint32_t PCROP2ER
Definition: stm32g474xx.h:473
FLASH_TypeDef::WRP1AR
__IO uint32_t WRP1AR
Definition: stm32g474xx.h:469
FLASH_TypeDef::WRP2AR
__IO uint32_t WRP2AR
Definition: stm32g474xx.h:474
FLASH_TypeDef::WRP1BR
__IO uint32_t WRP1BR
Definition: stm32g474xx.h:470
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32g474xx.h:460
FLASH_TypeDef::SEC1R
__IO uint32_t SEC1R
Definition: stm32g474xx.h:477
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32g474xx.h:458
FLASH_TypeDef::PCROP1SR
__IO uint32_t PCROP1SR
Definition: stm32g474xx.h:467
FLASH_TypeDef::PCROP1ER
__IO uint32_t PCROP1ER
Definition: stm32g474xx.h:468
FLASH_TypeDef::WRP2BR
__IO uint32_t WRP2BR
Definition: stm32g474xx.h:475
FLASH_TypeDef::PDKEYR
__IO uint32_t PDKEYR
Definition: stm32g474xx.h:459
FLASH_TypeDef::SEC2R
__IO uint32_t SEC2R
Definition: stm32g474xx.h:478
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:463
FLASH_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32g474xx.h:464
FLASH_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32g474xx.h:465
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:462
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32g474xx.h:461
FMAC_TypeDef
FMAC.
Definition: stm32g474xx.h:485
FMAC_TypeDef::WDATA
__IO uint32_t WDATA
Definition: stm32g474xx.h:492
FMAC_TypeDef::X2BUFCFG
__IO uint32_t X2BUFCFG
Definition: stm32g474xx.h:487
FMAC_TypeDef::X1BUFCFG
__IO uint32_t X1BUFCFG
Definition: stm32g474xx.h:486
FMAC_TypeDef::PARAM
__IO uint32_t PARAM
Definition: stm32g474xx.h:489
FMAC_TypeDef::YBUFCFG
__IO uint32_t YBUFCFG
Definition: stm32g474xx.h:488
FMAC_TypeDef::RDATA
__IO uint32_t RDATA
Definition: stm32g474xx.h:493
FMAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:490
FMAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:491
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32g474xx.h:501
FMC_Bank1_TypeDef::PCSCNTR
__IO uint32_t PCSCNTR
Definition: stm32g474xx.h:503
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32g474xx.h:511
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32g474xx.h:520
FMC_Bank3_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32g474xx.h:521
FMC_Bank3_TypeDef::PMEM
__IO uint32_t PMEM
Definition: stm32g474xx.h:523
FMC_Bank3_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32g474xx.h:526
FMC_Bank3_TypeDef::PATT
__IO uint32_t PATT
Definition: stm32g474xx.h:524
FMC_Bank3_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:522
FMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32g474xx.h:525
GPIO_TypeDef
General Purpose I/O.
Definition: stm32g474xx.h:534
GPIO_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32g474xx.h:544
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32g474xx.h:542
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32g474xx.h:535
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32g474xx.h:537
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32g474xx.h:539
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32g474xx.h:536
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32g474xx.h:538
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32g474xx.h:540
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32g474xx.h:541
HRTIM_Common_TypeDef
Definition: stm32g474xx.h:1079
HRTIM_Common_TypeDef::ADCUR
__IO uint32_t ADCUR
Definition: stm32g474xx.h:1111
HRTIM_Common_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32g474xx.h:1083
HRTIM_Common_TypeDef::DLLCR
__IO uint32_t DLLCR
Definition: stm32g474xx.h:1099
HRTIM_Common_TypeDef::ADCER
__IO uint32_t ADCER
Definition: stm32g474xx.h:1110
HRTIM_Common_TypeDef::ADC2R
__IO uint32_t ADC2R
Definition: stm32g474xx.h:1096
HRTIM_Common_TypeDef::ADCPS2
__IO uint32_t ADCPS2
Definition: stm32g474xx.h:1113
HRTIM_Common_TypeDef::EECR2
__IO uint32_t EECR2
Definition: stm32g474xx.h:1093
HRTIM_Common_TypeDef::EECR1
__IO uint32_t EECR1
Definition: stm32g474xx.h:1092
HRTIM_Common_TypeDef::EECR3
__IO uint32_t EECR3
Definition: stm32g474xx.h:1094
HRTIM_Common_TypeDef::BMCR
__IO uint32_t BMCR
Definition: stm32g474xx.h:1088
HRTIM_Common_TypeDef::BMCMPR
__IO uint32_t BMCMPR
Definition: stm32g474xx.h:1090
HRTIM_Common_TypeDef::IER
__IO uint32_t IER
Definition: stm32g474xx.h:1084
HRTIM_Common_TypeDef::BDTAUPR
__IO uint32_t BDTAUPR
Definition: stm32g474xx.h:1103
HRTIM_Common_TypeDef::BDTBUPR
__IO uint32_t BDTBUPR
Definition: stm32g474xx.h:1104
HRTIM_Common_TypeDef::ODISR
__IO uint32_t ODISR
Definition: stm32g474xx.h:1086
HRTIM_Common_TypeDef::ADC4R
__IO uint32_t ADC4R
Definition: stm32g474xx.h:1098
HRTIM_Common_TypeDef::BDTCUPR
__IO uint32_t BDTCUPR
Definition: stm32g474xx.h:1105
HRTIM_Common_TypeDef::BDTDUPR
__IO uint32_t BDTDUPR
Definition: stm32g474xx.h:1106
HRTIM_Common_TypeDef::BDMADR
__IO uint32_t BDMADR
Definition: stm32g474xx.h:1108
HRTIM_Common_TypeDef::BMTRGR
__IO uint32_t BMTRGR
Definition: stm32g474xx.h:1089
HRTIM_Common_TypeDef::FLTINR1
__IO uint32_t FLTINR1
Definition: stm32g474xx.h:1100
HRTIM_Common_TypeDef::FLTINR4
__IO uint32_t FLTINR4
Definition: stm32g474xx.h:1115
HRTIM_Common_TypeDef::ADC1R
__IO uint32_t ADC1R
Definition: stm32g474xx.h:1095
HRTIM_Common_TypeDef::BDMUPR
__IO uint32_t BDMUPR
Definition: stm32g474xx.h:1102
HRTIM_Common_TypeDef::ADCPS1
__IO uint32_t ADCPS1
Definition: stm32g474xx.h:1112
HRTIM_Common_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32g474xx.h:1080
HRTIM_Common_TypeDef::BDTEUPR
__IO uint32_t BDTEUPR
Definition: stm32g474xx.h:1107
HRTIM_Common_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32g474xx.h:1082
HRTIM_Common_TypeDef::BDTFUPR
__IO uint32_t BDTFUPR
Definition: stm32g474xx.h:1109
HRTIM_Common_TypeDef::ODSR
__IO uint32_t ODSR
Definition: stm32g474xx.h:1087
HRTIM_Common_TypeDef::ADC3R
__IO uint32_t ADC3R
Definition: stm32g474xx.h:1097
HRTIM_Common_TypeDef::BMPER
__IO uint32_t BMPER
Definition: stm32g474xx.h:1091
HRTIM_Common_TypeDef::FLTINR2
__IO uint32_t FLTINR2
Definition: stm32g474xx.h:1101
HRTIM_Common_TypeDef::FLTINR3
__IO uint32_t FLTINR3
Definition: stm32g474xx.h:1114
HRTIM_Common_TypeDef::OENR
__IO uint32_t OENR
Definition: stm32g474xx.h:1085
HRTIM_Common_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32g474xx.h:1081
HRTIM_Master_TypeDef
Definition: stm32g474xx.h:1026
HRTIM_Master_TypeDef::MCNTR
__IO uint32_t MCNTR
Definition: stm32g474xx.h:1031
HRTIM_Master_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32g474xx.h:1027
HRTIM_Master_TypeDef::MICR
__IO uint32_t MICR
Definition: stm32g474xx.h:1029
HRTIM_Master_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32g474xx.h:1028
HRTIM_Master_TypeDef::MREP
__IO uint32_t MREP
Definition: stm32g474xx.h:1033
HRTIM_Master_TypeDef::MCMP3R
__IO uint32_t MCMP3R
Definition: stm32g474xx.h:1037
HRTIM_Master_TypeDef::MCMP2R
__IO uint32_t MCMP2R
Definition: stm32g474xx.h:1036
HRTIM_Master_TypeDef::MPER
__IO uint32_t MPER
Definition: stm32g474xx.h:1032
HRTIM_Master_TypeDef::MDIER
__IO uint32_t MDIER
Definition: stm32g474xx.h:1030
HRTIM_Master_TypeDef::MCMP4R
__IO uint32_t MCMP4R
Definition: stm32g474xx.h:1038
HRTIM_Master_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32g474xx.h:1035
HRTIM_Master_TypeDef::MCMP1R
__IO uint32_t MCMP1R
Definition: stm32g474xx.h:1034
HRTIM_Timerx_TypeDef
Definition: stm32g474xx.h:1044
HRTIM_Timerx_TypeDef::TIMxCR
__IO uint32_t TIMxCR
Definition: stm32g474xx.h:1045
HRTIM_Timerx_TypeDef::SETx2R
__IO uint32_t SETx2R
Definition: stm32g474xx.h:1062
HRTIM_Timerx_TypeDef::CMP3xR
__IO uint32_t CMP3xR
Definition: stm32g474xx.h:1055
HRTIM_Timerx_TypeDef::OUTxR
__IO uint32_t OUTxR
Definition: stm32g474xx.h:1070
HRTIM_Timerx_TypeDef::RSTxR
__IO uint32_t RSTxR
Definition: stm32g474xx.h:1066
HRTIM_Timerx_TypeDef::SETx1R
__IO uint32_t SETx1R
Definition: stm32g474xx.h:1060
HRTIM_Timerx_TypeDef::CMP1CxR
__IO uint32_t CMP1CxR
Definition: stm32g474xx.h:1053
HRTIM_Timerx_TypeDef::TIMxISR
__IO uint32_t TIMxISR
Definition: stm32g474xx.h:1046
HRTIM_Timerx_TypeDef::TIMxICR
__IO uint32_t TIMxICR
Definition: stm32g474xx.h:1047
HRTIM_Timerx_TypeDef::CPT2xCR
__IO uint32_t CPT2xCR
Definition: stm32g474xx.h:1069
HRTIM_Timerx_TypeDef::RSTx2R
__IO uint32_t RSTx2R
Definition: stm32g474xx.h:1063
HRTIM_Timerx_TypeDef::EEFxR1
__IO uint32_t EEFxR1
Definition: stm32g474xx.h:1064
HRTIM_Timerx_TypeDef::PERxR
__IO uint32_t PERxR
Definition: stm32g474xx.h:1050
HRTIM_Timerx_TypeDef::CPT1xCR
__IO uint32_t CPT1xCR
Definition: stm32g474xx.h:1068
HRTIM_Timerx_TypeDef::RSTx1R
__IO uint32_t RSTx1R
Definition: stm32g474xx.h:1061
HRTIM_Timerx_TypeDef::EEFxR3
__IO uint32_t EEFxR3
Definition: stm32g474xx.h:1073
HRTIM_Timerx_TypeDef::DTxR
__IO uint32_t DTxR
Definition: stm32g474xx.h:1059
HRTIM_Timerx_TypeDef::FLTxR
__IO uint32_t FLTxR
Definition: stm32g474xx.h:1071
HRTIM_Timerx_TypeDef::CMP2xR
__IO uint32_t CMP2xR
Definition: stm32g474xx.h:1054
HRTIM_Timerx_TypeDef::TIMxDIER
__IO uint32_t TIMxDIER
Definition: stm32g474xx.h:1048
HRTIM_Timerx_TypeDef::CNTxR
__IO uint32_t CNTxR
Definition: stm32g474xx.h:1049
HRTIM_Timerx_TypeDef::CMP4xR
__IO uint32_t CMP4xR
Definition: stm32g474xx.h:1056
HRTIM_Timerx_TypeDef::CHPxR
__IO uint32_t CHPxR
Definition: stm32g474xx.h:1067
HRTIM_Timerx_TypeDef::EEFxR2
__IO uint32_t EEFxR2
Definition: stm32g474xx.h:1065
HRTIM_Timerx_TypeDef::CPT2xR
__IO uint32_t CPT2xR
Definition: stm32g474xx.h:1058
HRTIM_Timerx_TypeDef::REPxR
__IO uint32_t REPxR
Definition: stm32g474xx.h:1051
HRTIM_Timerx_TypeDef::CPT1xR
__IO uint32_t CPT1xR
Definition: stm32g474xx.h:1057
HRTIM_Timerx_TypeDef::TIMxCR2
__IO uint32_t TIMxCR2
Definition: stm32g474xx.h:1072
HRTIM_Timerx_TypeDef::CMP1xR
__IO uint32_t CMP1xR
Definition: stm32g474xx.h:1052
HRTIM_TypeDef
Definition: stm32g474xx.h:1119
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32g474xx.h:552
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32g474xx.h:555
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32g474xx.h:560
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32g474xx.h:557
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition: stm32g474xx.h:558
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32g474xx.h:562
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32g474xx.h:553
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32g474xx.h:559
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32g474xx.h:556
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32g474xx.h:563
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition: stm32g474xx.h:561
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32g474xx.h:554
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32g474xx.h:571
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32g474xx.h:572
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32g474xx.h:574
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition: stm32g474xx.h:576
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:575
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32g474xx.h:573
LPTIM_TypeDef
LPTIMER.
Definition: stm32g474xx.h:584
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32g474xx.h:586
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition: stm32g474xx.h:590
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32g474xx.h:588
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32g474xx.h:592
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition: stm32g474xx.h:587
LPTIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32g474xx.h:593
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32g474xx.h:585
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:589
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32g474xx.h:591
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32g474xx.h:601
OPAMP_TypeDef::TCMR
__IO uint32_t TCMR
Definition: stm32g474xx.h:604
OPAMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32g474xx.h:602
PWR_TypeDef
Power Control.
Definition: stm32g474xx.h:612
PWR_TypeDef::PUCRG
__IO uint32_t PUCRG
Definition: stm32g474xx.h:633
PWR_TypeDef::CR5
__IO uint32_t CR5
Definition: stm32g474xx.h:636
PWR_TypeDef::PDCRD
__IO uint32_t PDCRD
Definition: stm32g474xx.h:628
PWR_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32g474xx.h:620
PWR_TypeDef::PDCRB
__IO uint32_t PDCRB
Definition: stm32g474xx.h:624
PWR_TypeDef::PDCRA
__IO uint32_t PDCRA
Definition: stm32g474xx.h:622
PWR_TypeDef::PDCRE
__IO uint32_t PDCRE
Definition: stm32g474xx.h:630
PWR_TypeDef::PUCRC
__IO uint32_t PUCRC
Definition: stm32g474xx.h:625
PWR_TypeDef::SCR
__IO uint32_t SCR
Definition: stm32g474xx.h:619
PWR_TypeDef::PUCRF
__IO uint32_t PUCRF
Definition: stm32g474xx.h:631
PWR_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32g474xx.h:618
PWR_TypeDef::PDCRC
__IO uint32_t PDCRC
Definition: stm32g474xx.h:626
PWR_TypeDef::PUCRD
__IO uint32_t PUCRD
Definition: stm32g474xx.h:627
PWR_TypeDef::PDCRG
__IO uint32_t PDCRG
Definition: stm32g474xx.h:634
PWR_TypeDef::CR4
__IO uint32_t CR4
Definition: stm32g474xx.h:616
PWR_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32g474xx.h:613
PWR_TypeDef::PUCRB
__IO uint32_t PUCRB
Definition: stm32g474xx.h:623
PWR_TypeDef::PUCRE
__IO uint32_t PUCRE
Definition: stm32g474xx.h:629
PWR_TypeDef::PDCRF
__IO uint32_t PDCRF
Definition: stm32g474xx.h:632
PWR_TypeDef::SR1
__IO uint32_t SR1
Definition: stm32g474xx.h:617
PWR_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32g474xx.h:615
PWR_TypeDef::PUCRA
__IO uint32_t PUCRA
Definition: stm32g474xx.h:621
PWR_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32g474xx.h:614
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32g474xx.h:644
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32g474xx.h:651
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32g474xx.h:653
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32g474xx.h:652
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32g474xx.h:648
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32g474xx.h:650
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32g474xx.h:649
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32g474xx.h:654
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32g474xx.h:655
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32g474xx.h:656
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:645
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32g474xx.h:657
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32g474xx.h:646
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:647
RCC_TypeDef
Reset and Clock Control.
Definition: stm32g474xx.h:665
RCC_TypeDef::CCIPR
__IO uint32_t CCIPR
Definition: stm32g474xx.h:700
RCC_TypeDef::ICSCR
__IO uint32_t ICSCR
Definition: stm32g474xx.h:667
RCC_TypeDef::APB1SMENR2
__IO uint32_t APB1SMENR2
Definition: stm32g474xx.h:697
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32g474xx.h:702
RCC_TypeDef::CIER
__IO uint32_t CIER
Definition: stm32g474xx.h:672
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32g474xx.h:684
RCC_TypeDef::APB1RSTR1
__IO uint32_t APB1RSTR1
Definition: stm32g474xx.h:680
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32g474xx.h:668
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32g474xx.h:678
RCC_TypeDef::APB2SMENR
__IO uint32_t APB2SMENR
Definition: stm32g474xx.h:698
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32g474xx.h:676
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32g474xx.h:675
RCC_TypeDef::RESERVED6
uint32_t RESERVED6
Definition: stm32g474xx.h:691
RCC_TypeDef::CICR
__IO uint32_t CICR
Definition: stm32g474xx.h:674
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32g474xx.h:685
RCC_TypeDef::CCIPR2
__IO uint32_t CCIPR2
Definition: stm32g474xx.h:705
RCC_TypeDef::APB1RSTR2
__IO uint32_t APB1RSTR2
Definition: stm32g474xx.h:681
RCC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32g474xx.h:695
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32g474xx.h:677
RCC_TypeDef::APB1ENR1
__IO uint32_t APB1ENR1
Definition: stm32g474xx.h:688
RCC_TypeDef::CRRCR
__IO uint32_t CRRCR
Definition: stm32g474xx.h:704
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32g474xx.h:703
RCC_TypeDef::AHB3SMENR
__IO uint32_t AHB3SMENR
Definition: stm32g474xx.h:694
RCC_TypeDef::AHB2SMENR
__IO uint32_t AHB2SMENR
Definition: stm32g474xx.h:693
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32g474xx.h:682
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:666
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32g474xx.h:683
RCC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32g474xx.h:671
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32g474xx.h:690
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32g474xx.h:686
RCC_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32g474xx.h:701
RCC_TypeDef::AHB1SMENR
__IO uint32_t AHB1SMENR
Definition: stm32g474xx.h:692
RCC_TypeDef::APB1SMENR1
__IO uint32_t APB1SMENR1
Definition: stm32g474xx.h:696
RCC_TypeDef::RESERVED5
uint32_t RESERVED5
Definition: stm32g474xx.h:687
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32g474xx.h:669
RCC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32g474xx.h:679
RCC_TypeDef::CIFR
__IO uint32_t CIFR
Definition: stm32g474xx.h:673
RCC_TypeDef::APB1ENR2
__IO uint32_t APB1ENR2
Definition: stm32g474xx.h:689
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32g474xx.h:670
RCC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32g474xx.h:699
RNG_TypeDef
RNG.
Definition: stm32g474xx.h:978
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32g474xx.h:981
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:979
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:980
RTC_TypeDef
Definition: stm32g474xx.h:722
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32g474xx.h:735
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32g474xx.h:737
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32g474xx.h:734
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32g474xx.h:733
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32g474xx.h:724
RTC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32g474xx.h:738
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32g474xx.h:741
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32g474xx.h:742
RTC_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32g474xx.h:744
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32g474xx.h:740
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32g474xx.h:732
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32g474xx.h:723
RTC_TypeDef::SCR
__IO uint32_t SCR
Definition: stm32g474xx.h:746
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32g474xx.h:725
RTC_TypeDef::ICSR
__IO uint32_t ICSR
Definition: stm32g474xx.h:726
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:729
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32g474xx.h:736
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32g474xx.h:739
RTC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32g474xx.h:731
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32g474xx.h:728
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32g474xx.h:727
RTC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32g474xx.h:745
RTC_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:743
RTC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32g474xx.h:730
SAI_Block_TypeDef
Definition: stm32g474xx.h:814
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition: stm32g474xx.h:822
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition: stm32g474xx.h:821
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32g474xx.h:815
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition: stm32g474xx.h:818
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition: stm32g474xx.h:817
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32g474xx.h:819
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:820
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32g474xx.h:816
SAI_TypeDef
Serial Audio Interface.
Definition: stm32g474xx.h:806
SAI_TypeDef::PDMDLY
__IO uint32_t PDMDLY
Definition: stm32g474xx.h:810
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32g474xx.h:807
SAI_TypeDef::PDMCR
__IO uint32_t PDMCR
Definition: stm32g474xx.h:809
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32g474xx.h:830
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32g474xx.h:836
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32g474xx.h:834
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32g474xx.h:838
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32g474xx.h:831
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32g474xx.h:837
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition: stm32g474xx.h:839
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32g474xx.h:835
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:833
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32g474xx.h:832
SYSCFG_TypeDef
System configuration controller.
Definition: stm32g474xx.h:847
SYSCFG_TypeDef::SWPR
__IO uint32_t SWPR
Definition: stm32g474xx.h:853
SYSCFG_TypeDef::CFGR1
__IO uint32_t CFGR1
Definition: stm32g474xx.h:849
SYSCFG_TypeDef::SKR
__IO uint32_t SKR
Definition: stm32g474xx.h:854
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32g474xx.h:848
SYSCFG_TypeDef::SCSR
__IO uint32_t SCSR
Definition: stm32g474xx.h:851
SYSCFG_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32g474xx.h:852
TAMP_TypeDef
Tamper and backup registers.
Definition: stm32g474xx.h:754
TAMP_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32g474xx.h:770
TAMP_TypeDef::BKP20R
__IO uint32_t BKP20R
Definition: stm32g474xx.h:787
TAMP_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32g474xx.h:773
TAMP_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32g474xx.h:784
TAMP_TypeDef::BKP30R
__IO uint32_t BKP30R
Definition: stm32g474xx.h:797
TAMP_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32g474xx.h:774
TAMP_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32g474xx.h:767
TAMP_TypeDef::BKP26R
__IO uint32_t BKP26R
Definition: stm32g474xx.h:793
TAMP_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32g474xx.h:760
TAMP_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32g474xx.h:786
TAMP_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32g474xx.h:763
TAMP_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32g474xx.h:785
TAMP_TypeDef::SCR
__IO uint32_t SCR
Definition: stm32g474xx.h:765
TAMP_TypeDef::IER
__IO uint32_t IER
Definition: stm32g474xx.h:761
TAMP_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32g474xx.h:776
TAMP_TypeDef::BKP29R
__IO uint32_t BKP29R
Definition: stm32g474xx.h:796
TAMP_TypeDef::BKP24R
__IO uint32_t BKP24R
Definition: stm32g474xx.h:791
TAMP_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32g474xx.h:780
TAMP_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32g474xx.h:779
TAMP_TypeDef::FLTCR
__IO uint32_t FLTCR
Definition: stm32g474xx.h:758
TAMP_TypeDef::BKP31R
__IO uint32_t BKP31R
Definition: stm32g474xx.h:798
TAMP_TypeDef::BKP25R
__IO uint32_t BKP25R
Definition: stm32g474xx.h:792
TAMP_TypeDef::BKP23R
__IO uint32_t BKP23R
Definition: stm32g474xx.h:790
TAMP_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32g474xx.h:769
TAMP_TypeDef::BKP22R
__IO uint32_t BKP22R
Definition: stm32g474xx.h:789
TAMP_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32g474xx.h:777
TAMP_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32g474xx.h:755
TAMP_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32g474xx.h:771
TAMP_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32g474xx.h:772
TAMP_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32g474xx.h:775
TAMP_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32g474xx.h:781
TAMP_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32g474xx.h:778
TAMP_TypeDef::BKP27R
__IO uint32_t BKP27R
Definition: stm32g474xx.h:794
TAMP_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32g474xx.h:783
TAMP_TypeDef::BKP21R
__IO uint32_t BKP21R
Definition: stm32g474xx.h:788
TAMP_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32g474xx.h:764
TAMP_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:762
TAMP_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32g474xx.h:768
TAMP_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32g474xx.h:757
TAMP_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32g474xx.h:782
TAMP_TypeDef::BKP28R
__IO uint32_t BKP28R
Definition: stm32g474xx.h:795
TAMP_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32g474xx.h:756
TIM_TypeDef
TIM.
Definition: stm32g474xx.h:862
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32g474xx.h:866
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32g474xx.h:870
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32g474xx.h:871
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32g474xx.h:868
TIM_TypeDef::ECR
__IO uint32_t ECR
Definition: stm32g474xx.h:885
TIM_TypeDef::TISEL
__IO uint32_t TISEL
Definition: stm32g474xx.h:886
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32g474xx.h:878
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32g474xx.h:865
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition: stm32g474xx.h:881
TIM_TypeDef::AF2
__IO uint32_t AF2
Definition: stm32g474xx.h:888
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32g474xx.h:880
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition: stm32g474xx.h:882
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32g474xx.h:872
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32g474xx.h:889
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32g474xx.h:879
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32g474xx.h:873
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32g474xx.h:875
TIM_TypeDef::AF1
__IO uint32_t AF1
Definition: stm32g474xx.h:887
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32g474xx.h:863
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32g474xx.h:892
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32g474xx.h:877
TIM_TypeDef::DTR2
__IO uint32_t DTR2
Definition: stm32g474xx.h:884
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32g474xx.h:876
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32g474xx.h:869
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition: stm32g474xx.h:883
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32g474xx.h:874
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32g474xx.h:891
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:867
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32g474xx.h:864
UCPD_TypeDef
UCPD.
Definition: stm32g474xx.h:1000
UCPD_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32g474xx.h:1007
UCPD_TypeDef::RX_ORDEXT2
__IO uint32_t RX_ORDEXT2
Definition: stm32g474xx.h:1015
UCPD_TypeDef::CFG2
__IO uint32_t CFG2
Definition: stm32g474xx.h:1002
UCPD_TypeDef::TX_ORDSET
__IO uint32_t TX_ORDSET
Definition: stm32g474xx.h:1008
UCPD_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32g474xx.h:1013
UCPD_TypeDef::RESERVED0
__IO uint32_t RESERVED0
Definition: stm32g474xx.h:1003
UCPD_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:1004
UCPD_TypeDef::CFG1
__IO uint32_t CFG1
Definition: stm32g474xx.h:1001
UCPD_TypeDef::RX_PAYSZ
__IO uint32_t RX_PAYSZ
Definition: stm32g474xx.h:1012
UCPD_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32g474xx.h:1010
UCPD_TypeDef::RX_ORDEXT1
__IO uint32_t RX_ORDEXT1
Definition: stm32g474xx.h:1014
UCPD_TypeDef::RX_ORDSET
__IO uint32_t RX_ORDSET
Definition: stm32g474xx.h:1011
UCPD_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32g474xx.h:1005
UCPD_TypeDef::TX_PAYSZ
__IO uint32_t TX_PAYSZ
Definition: stm32g474xx.h:1009
UCPD_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:1006
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32g474xx.h:899
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32g474xx.h:903
USART_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32g474xx.h:908
USART_TypeDef::TDR
__IO uint32_t TDR
Definition: stm32g474xx.h:910
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32g474xx.h:904
USART_TypeDef::RDR
__IO uint32_t RDR
Definition: stm32g474xx.h:909
USART_TypeDef::RQR
__IO uint32_t RQR
Definition: stm32g474xx.h:906
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32g474xx.h:900
USART_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32g474xx.h:907
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32g474xx.h:902
USART_TypeDef::PRESC
__IO uint32_t PRESC
Definition: stm32g474xx.h:911
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition: stm32g474xx.h:905
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32g474xx.h:901
USB_TypeDef
Universal Serial Bus Full Speed Device.
Definition: stm32g474xx.h:919
USB_TypeDef::BTABLE
__IO uint16_t BTABLE
Definition: stm32g474xx.h:944
USB_TypeDef::RESERVEDE
__IO uint16_t RESERVEDE
Definition: stm32g474xx.h:949
USB_TypeDef::EP1R
__IO uint16_t EP1R
Definition: stm32g474xx.h:922
USB_TypeDef::RESERVED4
__IO uint16_t RESERVED4
Definition: stm32g474xx.h:929
USB_TypeDef::RESERVEDD
__IO uint16_t RESERVEDD
Definition: stm32g474xx.h:947
USB_TypeDef::EP4R
__IO uint16_t EP4R
Definition: stm32g474xx.h:928
USB_TypeDef::EP0R
__IO uint16_t EP0R
Definition: stm32g474xx.h:920
USB_TypeDef::RESERVED2
__IO uint16_t RESERVED2
Definition: stm32g474xx.h:925
USB_TypeDef::CNTR
__IO uint16_t CNTR
Definition: stm32g474xx.h:936
USB_TypeDef::ISTR
__IO uint16_t ISTR
Definition: stm32g474xx.h:938
USB_TypeDef::EP5R
__IO uint16_t EP5R
Definition: stm32g474xx.h:930
USB_TypeDef::FNR
__IO uint16_t FNR
Definition: stm32g474xx.h:940
USB_TypeDef::RESERVED5
__IO uint16_t RESERVED5
Definition: stm32g474xx.h:931
USB_TypeDef::RESERVED3
__IO uint16_t RESERVED3
Definition: stm32g474xx.h:927
USB_TypeDef::RESERVEDB
__IO uint16_t RESERVEDB
Definition: stm32g474xx.h:943
USB_TypeDef::RESERVEDC
__IO uint16_t RESERVEDC
Definition: stm32g474xx.h:945
USB_TypeDef::RESERVEDA
__IO uint16_t RESERVEDA
Definition: stm32g474xx.h:941
USB_TypeDef::EP2R
__IO uint16_t EP2R
Definition: stm32g474xx.h:924
USB_TypeDef::RESERVED0
__IO uint16_t RESERVED0
Definition: stm32g474xx.h:921
USB_TypeDef::EP6R
__IO uint16_t EP6R
Definition: stm32g474xx.h:932
USB_TypeDef::EP7R
__IO uint16_t EP7R
Definition: stm32g474xx.h:934
USB_TypeDef::RESERVED1
__IO uint16_t RESERVED1
Definition: stm32g474xx.h:923
USB_TypeDef::EP3R
__IO uint16_t EP3R
Definition: stm32g474xx.h:926
USB_TypeDef::RESERVED9
__IO uint16_t RESERVED9
Definition: stm32g474xx.h:939
USB_TypeDef::RESERVED8
__IO uint16_t RESERVED8
Definition: stm32g474xx.h:937
USB_TypeDef::LPMCSR
__IO uint16_t LPMCSR
Definition: stm32g474xx.h:946
USB_TypeDef::DADDR
__IO uint16_t DADDR
Definition: stm32g474xx.h:942
USB_TypeDef::RESERVED6
__IO uint16_t RESERVED6
Definition: stm32g474xx.h:933
USB_TypeDef::BCDR
__IO uint16_t BCDR
Definition: stm32g474xx.h:948
VREFBUF_TypeDef
VREFBUF.
Definition: stm32g474xx.h:957
VREFBUF_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32g474xx.h:959
VREFBUF_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32g474xx.h:958
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32g474xx.h:967
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32g474xx.h:968
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32g474xx.h:969
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32g474xx.h:970
system_stm32g4xx.h
CMSIS Cortex-M4 Device System Source File for STM32G4xx devices.
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